Datasheet > PLL2080X

PLL2080X

更新时间： 2024-09-20 23:28:43

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PLL2080X 0.35um40MHz De-Skew PLL PLL2080X\|Data Sheet

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PLL2080X 数据手册

§•

0.35 40MHz De-Skew PLL

PLL2080X

DECEMBER 1998. Ver1.0

40MHz PLL ASIC Core

The PLL2080X PLL is an application specific PLL designed for the requirements of one customer.

The core PLL is a standard 80MHz ring oscillator design with a phase frequency detector. Divide

ratios and feedback paths are designed specific to the customers needs.

Features

• 3.3V operations in the Samsung 0.35um process

• Core PLL jitter less than ± 200ps

• 20MHz clock input matched in phase to 40MHz clock output

• Selectable feedback matching paths

Functional Block Diagram

CLKIN

MODE

Charge

Pump

Clock

Input

Matched

Delay

PFD

REFCLK

RCPLL

Divide 2

Clock

Tree

Matched

Delay

VCO

Differential

Ring Oscillator

Divide 2

CLKOUT

Figure 1. Functional Block Diagram

Pin Description

Pin Name

Description

VDD

VSS

3.3V ± 5% PLL Supply

0V PLL Ground

CLKIN

External Clock Input to PLL

Duty Cycle : 40%~60%

REFCLK

CLKOUT

MODE

Feedback clock input to PLL from reference point on internal device clock tree

PLL output clock

Mode=1, select to REFCLK / Mode=0, select to Match Delay

Point of connection to external discrete loop filter

RCPLL

1 / 5

12 3 4 5

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