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PLL205-01XI PDF预览

PLL205-01XI

更新时间: 2024-09-21 10:08:39
品牌 Logo 应用领域
其他 - ETC 时钟发生器
页数 文件大小 规格书
12页 103K
描述
Motherboard Clock Generator for AMD - K7

PLL205-01XI 数据手册

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PLL205-01  
Motherboard Clock Generator for AMD - K7  
FEATURES  
PIN CONFIGURATION  
·
Generates all clock frequencies for VIA K7 chip  
sets requiring multiple CPU clocks and high  
speed SDRAM buffers.  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDD0  
REF0//CPU_STOP#^  
REF1/FS2*^  
GND  
CPUT1  
GND  
CPUC0  
CPUT0  
2
3
GND  
XIN  
XOUT  
VDD1  
4
·
Support one pair of differential CPU clocks, one  
open-drain CPU, 6 PCI and 13 high-speed  
SDRAM buffers for 3-DIMM applications.  
5
6
7
VDD3  
PD#^  
PCI5/MODE*^  
PCI0/FS3*^  
GND  
8
9
SDRAM12  
GND  
SDRAM0  
SDRAM1  
VDD3  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDD3  
SDRAM6  
SDRAM7  
VDD4  
48MHz/FS0*^  
24_48MHz/FS1*^  
·
·
·
One 24_48MHz clock and one 48MHz clock.  
Two14.318MHz reference clocks.  
Power management control to stop CPU, and  
Power down Mode from I2C programming.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
PCI1/SEL24_48*^  
PCI2  
PCI3  
PCI4  
VDD2  
SDRAMIN  
GND  
SDRAM11  
SDRAM10  
VDD3  
SDRAM9  
SDRAM8  
GND  
SDATA  
SCLK  
·
·
·
Support 2-wire I2C serial bus interface with built-  
in Vendor ID, Device ID and Revision ID.  
Single byte micro-step linear Frequency Progra-  
mming via I2C with Glitch free smooth switching.  
Spread Spectrum ±0.25% center spread, 0 to  
- 0.5% downspread.  
·
·
50% duty cycle with low jitter.  
Available in 300 mil 48 pin SSOP.  
Note: ^: Pull up, #: Active Low  
*: Bi-directional latched at power-up  
BLOCK DIAGRAM  
I/O MODE CONFIGURATION  
MODE (Pin 7)  
1 (OUTPUT)  
0 (INPUT)  
PIN 2  
REF0  
VDD1  
XIN  
XTAL  
OSC  
REF(0:1)  
CPU_STOP  
XOUT  
CPUT(0:1)  
CPUC0  
POWER GROUP  
·
·
·
·
·
VDD0: PLL CORE  
I2C  
Logic  
SDATA  
SCLK  
VDD1: REF(0:1), XIN, XOUT  
VDD2: PCI(0:5)  
Control  
Logic  
FS (0:3)*  
VDD2  
PCI(0:4)  
VDD3: SDRAM(0:12)  
VDD4: 48MHz, 24_48MHz  
PLL1  
SST  
PCI5  
VDD4  
PD  
KEY SPECIFICATIONS  
48Mhz  
PLL2  
·
·
·
·
·
CPU Cycle to Cycle jitter: 250ps.  
24_48Mhz  
¸ 2  
VDD3  
PCI to PCI output skew: 500ps.  
SDRAM(0:11)  
CPU to CPU output skew: ±175ps  
SDRAM to SDRAM output skew: 250ps.  
CPU to PCI skew (CPU leads): 0 ~ 3 ns.  
SDRAMIN  
SDRAM12  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 03/07/00 Page 1  

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