Datasheet > PLL2026X

PLL2026X

更新时间： 2024-09-20 23:28:43

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PLL2026X 25MHz ~ 300MHz FSPLL PLL2026X\|Data Sheet

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PLL2026X 数据手册

25MHz ~ 300MHz FSPLL

PLL2026X

February 2000 V2.0

General Description

Features

The PLL2026X is a Phase-Locked Loop (PLL) frequency synthesizer

constructed in CMOS process technology. The PLL macrofunctions

provide frequency multiplication capabilities.The output clock frequency

Fout is related to the reference input clock frequency, by the follwing

equation:

• 0.25um CMOS process technology

• 2.5 Volt Single power supply

• Output frequency range: 25MHz~300 MHz

• Cycle-to-cycle jitter: ±…100ps

• Output Duty ratio: 40% to 60%

• Input Duty ratio: 30% to 70%

• Frequency changed by programmable divider

• Power down mode

Fout=( m*Fin ) / ( p*s )

where Fout is the output clock frequency. Fin is the reference input

clock frequency. m,p and s are the values for programmable dividers.

PLL2026X consists of a Phase/Frequency Detector(PFD), a Charge

Pump an External Loop Filter, a Voltage Controlled Oscillator(VCO),

a 6bit Pre-divider, an 8bit Main divider and 2bit Post Scaler as

shown in Figure 1.

• Lock Detector mode

FUNCTIONAL BLOCK DIAGRAM

LDT

FIN

FOUT

Pre Divider

Charge

Pump

Post Scaler

VCO

PFD

FILTER

Main Divider

PWRDN

P[5]~P[0]

M[7]~M[0]

S[1],S[0]

AVSS25A

AVSS25D

AVDD25A

AVDD25D

AVBB25

Figure 1. Functional Block Diagram

1 / 6

12 3 4 5 6

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