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PI74FCT162H240DTV PDF预览

PI74FCT162H240DTV

更新时间: 2024-09-12 20:26:39
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百利通 - PERICOM /
页数 文件大小 规格书
6页 63K
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PI74FCT162H240DTV 数据手册

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PI74FCT16240T  
PI74FCT162240T  
PI74FCT162H240T  
Fast CMOS 16-Bit  
Buffer/Line Drivers  
ProductFeatures:  
CommonFeatures:  
• PI74FCT16240T,PI74FCT162240T,andPI74FCT162H240T  
are high-speed,  
low power devices with high current drive  
• VCC =5V±10%  
Product Description:  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.6 micron CMOS technology,  
achieving industry leading speed grades.  
• Hysteresis on all inputs  
• Packagesavailable:  
48-pin240milwideplasticTSSOP(A)  
48-pin300milwideplasticSSOP(V)  
PI74FCT16240TFeatures:  
• High output drive: IOH = –32 mA; IOL = 64 mA  
• Power off disable outputs permit "live insertion"  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
ThePI74FCT16240T,PI74FCT162240T,andPI74FCT162H240T  
are inverting 16-bit buffer/line drivers designed for applications  
driving high capacitance loads and low impedance backplanes.  
Thesehigh-speed,lowpowerdevicesofferbus/backplaneinterface  
capabilityandaflow-throughorganizationforeaseofboardlayout.  
These devices are designed with three-state controls to operate in  
a Quad-Nibble, Dual-Byte, or a single 16-bit word mode.  
The PI74FCT16240T output buffers are designed with a Power-  
Off disable allowing “live insertion” of boards when used as  
backplane drivers.  
PI74FCT162240TFeatures:  
The PI74FCT162240T has ±24 mA balanced output drivers. It is  
designed with current limiting resistors at its outputs to control the  
output edge rate resulting in lower ground bounce and undershoot.  
This eliminates the need for external terminating resistors for most  
interface applications.  
• Balanced output drivers: ±24 mA  
• Reduced system switching noise  
• Typical VOLP (Output Ground Bounce) < 0.6V  
atVCC =5V,TA =25°C  
PI74FCT162H240TFeatures:  
The PI74FCT162H240T has “Bus Hold” which retains the input's  
last state whenever the input goes to high-impedance preventing  
“floatinginputsandeliminatingtheneedforpull-up/downresistors.  
• Bus Hold retains last active bus state during 3-state  
• Eliminates the need for external pull-up resistors  
Logic Block Diagram  
1OE  
3OE  
1A0  
1A1  
1A2  
1A3  
1Y0  
1Y1  
1Y2  
1Y3  
3A0  
3A1  
3A2  
3A3  
3Y0  
3Y1  
3Y2  
3Y3  
2OE  
4OE  
2A0  
2A1  
2A2  
2A3  
2Y0  
2Y1  
2Y2  
2Y3  
4A0  
4A1  
4A2  
4A3  
4Y0  
4Y1  
4Y2  
4Y3  
PS2030A 03/11/96  
1

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