PI74FCT16244/162244/162H244T
PI74FCT16244T
16-BIT BUFFER/LINE DRIVERS
PI74FCT162244T
PI74FCT162H244T
Fast CMOS 16-Bit
Buffer/Line Drivers
Product Features:
Common Features:
• PI74FCT16244T, PI74FCT162244T and
PI74FCT162H244T are high-speed, low power devices
with high current drive.
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
• Vcc = 5V ±10%
• Hysteresis on all inputs
• Packages available:
ThePI74FCT16244T,PI74FCT162244T,andPI74FCT162H244T
arenon-inverting16-bitbuffer/linedriversdesignedforapplications
driving high capacitance loads and low impedance backplanes.
Thesehigh-speed,lowpowerdevicesofferbus/backplaneinterface
capabilityandaflow-throughorganizationforeaseofboardlayout.
These devices are designed with three-state controls to operate in a
Quad-Nibble, Dual-Byte, or a single 16-bit word mode.
– 48-pin 240 mil wide plastic TSSOP (A48)
– 48-pin 300 mil wide plastic SSOP (V48)
• Device models available upon request.
PI74FCT16244T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
ThePI74FCT16244ToutputbuffersaredesignedwithaPower-Off
disable allowing "live insertion" of boards when used as backplane
drivers.
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162244T Features:
The PI74FCT162244T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
at VCC = 5V, TA = 25°C
PI74FCT162H244T Features:
The PI74FCT162H244T has "Bus Hold" which retains the input's
last state whenever the input goes to high-impedance preventing
"floating"inputsandeliminatingtheneedforpull-up/downresistors.
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
Logic Block Diagram
1OE
3OE
1A
1A
1A
1
A
0
1
2
3
1Y0
1Y1
1Y2
Y
1 3
3A
3A
3A
3
A
0
1
2
3
3Y
3Y
3Y
3
Y
0
1
2
3
2OE
4OE
2A
2A
2A
2
A
0
1
2
3
2Y0
2Y1
2Y2
Y
2 3
4A
4A
4A
4
A
0
1
2
3
4Y
4Y
4Y
4
Y
0
1
2
3
PS2031A 03/11/96
161