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PI74FCT162501ETV PDF预览

PI74FCT162501ETV

更新时间: 2024-10-27 23:27:39
品牌 Logo 应用领域
其他 - ETC 总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 305K
描述
18-Bit Bus Transceiver

PI74FCT162501ETV 数据手册

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PI74FCT16501T
PI74FCT162501T
PI74FCT162H501T  
Fast CMOS 18-Bit  
Registered Transceivers  
ProductFeatures  
CommonFeatures:  
ProductDescription  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.6 micron CMOS technology,  
achieving industry leading speed grades.  
• PI74FCT16501T,PI74FCT162501T,andPI74FCT162H501T  
are high-speed,  
low power devices with high current drive.  
ThePI74FCT16501T,PI74FCT162501T,andPI74FCT162H501Tare  
18-bit registered bus transceivers designed with D-type latches and  
flip-flops to allow data flow in transparent, latched, and clocked  
modes.TheOutputEnable(OEABandOEBA,LatchEnable(LEAB  
andLEBA)andClock(CLKABandCLKBA)inputscontrolthedata  
flowineachdirection.WhenLEABisHIGH,thedeviceoperatesin  
transparentmodeforA-to-Bdataflow. WhenLEABisLOW,theA  
dataislatchedifCLKABisheldataHIGHorLOWlogiclevel. The  
A bus data is stored in the latch/flip-flop on the LOW-to-HIGH  
transitionofCLKAB,ifLEABisLOW.OEABperformstheoutput  
enablefunctionontheBport. DataflowfromBporttoAportissimilar  
using OEBA, LEBA and CLKBA. These high-speed, low power  
devices offer a flow-through organization for ease of board layout.  
• VCC =5V±10%  
• Hysteresis on all inputs  
• Packages available  
–56-pin240milwideplasticTSSOP(A)  
–56-pin300milwideplasticSSOP(V)  
PI74FCT16501TFeatures  
• High output drive: IOH = –32 mA; IOL = 64 mA  
• Power off disable outputs permit “live insertion”  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
ThePI74FCT16501ToutputbuffersaredesignedwithaPower-Off  
disable allowing "live insertion" of boards when used as backplane  
drivers.  
PI74FCT162501TFeatures  
• Balanced output drivers: ±24 mA  
• Reduced system switching noise  
The PI74FCT162501T has ±24 mA balanced output drivers. It is  
designed with current limiting resistors at its outputs to control the  
output edge rate resulting in lower ground bounce and undershoot.  
This eliminates the need for external terminating resistors for most  
interface applications.  
• Typical VOLP (Output Ground Bounce) < 0.6V  
atVCC =5V,TA =25°C  
PI74FCT162H501TFeatures  
• Bus Hold retains last active bus state during 3-state  
• Eliminates the need for external pull-up resistors  
The PI74FCT162H501T has “Bus Hold” which retains the input’s  
last state whenever the input goes to high-impedance preventing  
“floating”inputsandeliminatingtheneedforpull-up/downresistors.  
Logic Block Diagram  
OEAB  
CLKBA  
LEBA  
OEBA  
CLKAB  
LEAB  
C
C
B1  
A1  
D
D
C
D
C
D
TO 17 OTHER CHANNELS  
PS2035A 03/11/96  
1

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