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PI74FCT162511ATV PDF预览

PI74FCT162511ATV

更新时间: 2024-10-27 23:27:39
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其他 - ETC 总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 395K
描述
16-Bit Bus Transceiver

PI74FCT162511ATV 数据手册

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PI74FCT16511T  
PI74FCT162511T  
Fast CMOS 16-Bit Registered/Latched  
Transceiver With Parity  
ProductFeatures  
ProductDescription  
CommonFeatures  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.8 micron CMOS technology,  
achieving industry leading speed grades.  
• PI74FCT16511andPI74FCT162511arehigh-speed,low  
power devices with high current drive.  
• Vcc=5V±10%  
• Typical tsk(o) (Output Skew) < 250ps, clocked mode  
• Extendedrangeof–40°Cto+85°C  
• Hysteresis on all inputs  
The PI74FCT16511T and PI74FCT162511T are high-speed, low-  
power 16-bit registered/latched transceiver with parity which  
combines D-type latches and D-type flip-flops to allow data flow in  
transparent, latched or clocked modes. It has a parity generator/  
checker in the A-to-B direction and a parity checker in the B-to-A  
direction.Errorcheckingisdoneatthebytelevelwithseparateparity  
bits for each byte. One error flag for each direction (A-to-B or B-to-  
A) exists to indicate an error for either byte in either direction. The  
parity error flags which are open drain outputs, can be tied together  
and/or tied with flags from other devices to form a single error flag  
orinterrupt.Todisabletheerrorflagduringcombinationaltransitions,  
adesignercandisabletheparityerrorflagbytheOExxcontrolpins.  
• Packagesavailable:  
–56-pin240milwideTSSOP(A)  
–56-pin300milwideSSOP(V)  
PI74FCT16511TFeatures  
• High output drive: IOH = –32mA; IOL = 64mA  
• Power off disable outputs permit “live insertion”  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
The operation in A-to-B direction is controlled by LEAB, CLKAB  
and OEAB control pins, and the operation in B-to-A direction is  
controlledbyLEBA,CLKBAandOEBAcontrolpins. GEN/CHKis  
used to select the operation of A-to-B direction, while B-to-A  
direction is always in checking mode. The ODD/EVEN select is  
commonbetweenthetwodirections. Independentoperationcanbe  
achieved between the two directions by using the corresponding  
controllinesexceptfortheODD/EVENcontrol.  
PI74FCT162511TFeatures  
• High output drive: IOL/IOH = 24mA  
• Opendrainparityerrorallowswire-OR  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
• Balanced output drivers: ±24mA  
• Series current limiting resistors  
Simplified Logic Block Diagram  
LEAB  
CLKAB  
OEAB  
Data  
Parity, data  
16  
B0-15  
18  
Parity  
2
Latch/  
Register  
PB1,2  
GEN/CHK  
Byte  
Parity  
Generator/  
Checker  
PERB  
(Open Drain)  
A0-15  
PA1,2  
ODD/EVEN  
LEBA  
CLKBA  
Parity, data  
18  
Parity, data  
18  
Latch/  
Register  
OEBA  
PERA  
Byte  
Parity  
Checking  
(Open Drain)  
PS2080A 01/15/95  
1

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