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PI74FCT162511ATVX PDF预览

PI74FCT162511ATVX

更新时间: 2024-02-01 02:51:33
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
8页 90K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, 0.300 INCH, SSOP-56

PI74FCT162511ATVX 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.45
其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B系列:FCT
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:18.415 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:16
功能数量:1端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):6 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

PI74FCT162511ATVX 数据手册

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PI74FCT16511T  
PI74FCT162511T  
Fast CMOS 16-Bit Registered/Latched  
Transceiver With Parity  
ProductFeatures:  
CommonFeatures:  
• PI74FCT16511andPI74FCT162511arehigh-speed,low  
power devices with high current drive.  
Product Description:  
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-  
duced in the Company’s advanced 0.8 micron CMOS technology,  
achieving industry leading speed grades.  
• Vcc=5V±10%  
• Typical tsk(o) (Output Skew) < 250 ps, clocked mode  
• Extendedrangeof40°Cto+85°C  
• Hysteresis on all inputs  
The PI74FCT16511T and PI74FCT162511T are high-speed, low-  
power 16-bit registered/latched transceiver with parity which  
combines D-type latches and D-type flip-flops to allow data flow  
in transparent, latched or clocked modes. It has a parity generator/  
checker in the A-to-B direction and a parity checker in the B-to-A  
direction. Error checking is done at the byte level with separate  
parity bits for each byte. One error flag for each direction (A-to-B  
or B-to-A) exists to indicate an error for either byte in either  
direction. The parity error flags which are open drain outputs, can  
be tied together and/or tied with flags from other devices to form a  
single error flag or interrupt. To disable the error flag during  
combinational transitions, a designer can disable the parity error  
flag by the OExx control pins.  
• Packagesavailable:  
56-pin240milwideTSSOP(A)  
56-pin300milwideSSOP(V)  
PI74FCT16511TFeatures:  
• High output drive: IOH = –32 mA; IOL = 64 mA  
• Power off disable outputs permit “live insertion”  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
PI74FCT162511TFeatures:  
• High output drive: IOL/IOH = 24 mA  
• Opendrainparityerrorallowswire-OR  
The operation in A-to-B direction is controlled by LEAB, CLKAB  
and OEAB control pins, and the operation in B-to-A direction is  
controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK  
is used to select the operation of A-to-B direction, while B-to-A  
direction is always in checking mode. The ODD/EVEN select is  
commonbetweenthetwodirections. Independentoperationcanbe  
achieved between the two directions by using the corresponding  
control lines except for the ODD/EVEN control.  
• Typical VOLP (Output Ground Bounce) < 1.0V  
atVCC =5V,TA =25°C  
• Balanced output drivers: ±24 mA  
• Series current limiting resistors  
Simplified Logic Block Diagram  
LEAB  
CLKAB  
OEAB  
Data  
Parity, data  
16  
B0-15  
18  
Parity  
2
Latch/  
Register  
PB1,2  
GEN/CHK  
Byte  
Parity  
Generator/  
Checker  
PERB  
(Open Drain)  
A0-15  
PA1,2  
ODD/EVEN  
LEBA  
CLKBA  
Parity, data  
18  
Parity, data  
18  
Latch/  
Register  
OEBA  
PERA  
Byte  
Parity  
Checking  
(Open Drain)  
PS2080A 01/15/95  
1

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