Datasheet > PF48F5000M0Y3C0

PF48F5000M0Y3C0

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
68页	1704K
描述
Memory IC

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数据手册

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PF48F5000M0Y3C0 数据手册

Intel StrataFlash^®Cellular Memory (M18)

2.0

Functional Description

The Functional Description includes the following sections:

• Product Overview

• Configuration and Memory Map

• Device ID

• Ordering Information

• Additional Information

2.1

Product Overview

The Intel StrataFlash^®Cellular Memory (M18) device provides high read and write

performance at low voltage on a 16-bit data bus.

The flash memory device has a multi-partition architecture with read-while-program

and read-while-erase capability.

The device supports synchronous burst reads up to 108 MHz using ADV# and CLK

address-latching on some litho/density combinations and up to 133 MHz using CLK

address-latching only on some litho/density combinations. It is listed below in the

following table.

Table 4.

M18 Product Litho/Density/Frequency Combinations

Litho (nm)

Density (Mbit)

Supports frequency up to (MHz)

Sync read address-latching

256

512

133

108

133

108

133

CLK-latching

ADV#- and CLK-latching

CLK-latching

128

256

CLK-latching

512

CLK-latching

1024

ADV#- and CLK-latching

CLK-latching

In continuous-burst mode, a data Read can traverse partition boundaries.

Upon initial power-up or return from reset, the device defaults to asynchronous array-

read mode. Synchronous burst-mode reads are enabled by programming the Read

Configuration Register. In synchronous burst mode, output data is synchronized with a

user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory

synchronization.

Designed for low-voltage applications, the device supports read operations with V_CCat

1.8 V, and erase and program operations with V_PPat 1.8 V or 9.0 V. VCC and VPP can

be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a

dedicated VPP connection provides complete data protection when V_PPis less than

V_PPLK

A Status Register provides status and error conditions of erase and program

operations.

One-Time-Programmable (OTP) registers allow unique flash device identification that

can be used to increase flash content security. Also, the individual block-lock feature

provides zero-latency block locking and unlocking to protect against unwanted program

or erase of the array.

Intel StrataFlash^®Cellular Memory (M18)

July 2007

Document Number: 309823-009US

1...5 6 789 10 11...68

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与PF48F5000M0Y3C0相关器件

型号	品牌	获取价格	描述	数据表
PF48F5000M0YBB0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA105,
PF48F5000M0YBC0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA107,
PF48F5000M0YCB0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA105,
PF48F5000M0YCC0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA107,
PF48F5000M0YUB0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA105,
PF48F5000M0YUC0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA107,
PF48F5000M0YWB0	NUMONYX	获取价格	Flash, 32MX16, 96ns, PBGA105,
PF48F6000M0Y0B0	NUMONYX	获取价格	Flash, 64MX16, 96ns, PBGA105,
PF48F6000M0Y0BE	INTEL	获取价格	Flash, 64MX16, 96ns, PBGA105, 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, SCSP-105
PF48F6000M0Y0BEA	INTEL	获取价格	Flash, 64MX16, PBGA105, 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, SCSP-105

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