Datasheet > PF48F5000M0Y3C0

PF48F5000M0Y3C0

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
68页	1704K
描述
Memory IC

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PF48F5000M0Y3C0 数据手册

Intel StrataFlash^®Cellular Memory (M18)

Table 31.

Voltage / NOR Flash CE# Configuration Decoder

I/O

Voltage

(Volt)

Code

Core Voltage (Volt)

CE# Configuration

3.0

1.8

Virtual Address

1.8

3.0

1.8

3.0

Virtual Address

Table 32.

Parameter / Mux Configuration Decoder

Code, Mux

Identificati

Number of Flash

Flash Die

Bus Width

Die

0 = Non Mux

1 = AD Mux

Notation used for stacks that contain no parameter

blocks

Any

3 = "Full" AD

Mux

Bottom

Top

B = Non Mux

C = AD Mux

X16

X32

X16

X32

Bottom

Top

Bottom

Top

F = "Full" Ad

Mux

Bottom

Top

T = Non Mux

U = AD Mux

Top

Bottom

Top

Bottom

Top

W = "Full" Ad

Mux

Top

Bottom

Top

Bottom

Top

Bottom

Table 33.

Ballout Decoder

Code

Ballout Definition

0 (Zero)

SDiscrete ballout (Easay BGA and TSOP)

x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus)

x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus)

QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus)

x32SH ballout, 106 ball (x32 NOR only Share Bus)

x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus

x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus

Intel StrataFlash^®Cellular Memory (M18)

July 2007

Document Number: 309823-009US

1...65 66 6768

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