Datasheet > PF48F5000M0Y3C0

PF48F5000M0Y3C0

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
68页	1704K
描述
Memory IC

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PF48F5000M0Y3C0 数据手册

Intel StrataFlash^®Cellular Memory (M18)

Figure 35.

Sync Read to Write (AD-Mux)

R311

R313

R306

W22

CLK [C]

R301

A[Max:16]

R305

R304

R305

A/DQ[15:0]

CE# [E]

R303

R11

R302

R316

W15

ADV# [V]

WE# [W]

OE# [G]

R307

High-Z

WAIT [T]

Notes:

CLK may be stopped during write cycle.

W22 is the time between the Address-latching-CLK and WE#. In case of ADV#-latching, W21 must be

met instead.

Figure 36.

Write to Sync Read (AD-Mux)

W19

CLK

A[Max:16]

R305

R304

R305

R304

R307

R305

A/DQ[15:0]

WAIT [T]

R15

R105

W15

W28

ADV# [V]

CE# [E]

R11

W22

W27

WE# [W]

OE# [G]

W14

Note: CLK may be stopped during write cycle.

Intel StrataFlash^®Cellular Memory (M18)

July 2007

Document Number: 309823-009US

1...59 60 616263 64 65...68

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