Datasheet > PF48F5000M0Y3C0

PF48F5000M0Y3C0

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
68页	1704K
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Memory IC

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PF48F5000M0Y3C0 数据手册

Intel StrataFlash^®Cellular Memory (M18)

7.6

Deep Power Down Specifications

Table 26.

Deep Power Down Specifications

Nbr.

Symbol

Parameter

DPD asserted pulse width

Min

Max

Unit

Notes

_{SLSH (}t_SHSL)

t_{EHSH ( EHSL)}

t_SHEL(t_SLEL)

100

—

1,2,3

1,2

CE# high to DPD asserted

DPD deasserted to CE# low

1,2

µs

RST# high during DPD state to CE# low (DPD

deasserted to CE# low)

t_PHEL

—

1,2

Notes:

These specifications are valid for all device versions (packages and speeds).

Sampled, but not 100% tested.

DPD must remain asserted for the duration of Deep Power Down mode. DPD current levels are achieved 40 µs after

entering the DPD mode.

Figure 38.

Deep Power Down Operation Timing

DPD [S]

CE# [E]

RST# [P]

Note: DPD pin is low-true (ECR14 = 0)

Figure 39.

Reset During Deep Power Down Operation Timing

RST# [P]

DPD [S]

CE# [E]

Note: DPD pin is low-true (ECR14 = 0)

Intel StrataFlash^®Cellular Memory (M18)

July 2007

Document Number: 309823-009US

1...62 63 646566 67 68

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