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PEX8524V PDF预览

PEX8524V

更新时间: 2024-11-10 06:00:19
品牌 Logo 应用领域
PLX 开关PC
页数 文件大小 规格书
4页 877K
描述
Flexible & Versatile PCI Express™ Switch

PEX8524V 数据手册

 浏览型号PEX8524V的Datasheet PDF文件第2页浏览型号PEX8524V的Datasheet PDF文件第3页浏览型号PEX8524V的Datasheet PDF文件第4页 
Version 1.4 2007  
PEX 8524V  
Flexible & Versatile PCI ExpressSwitch  
Features  
ƒ PEX 8524V General Features  
o 24-lane PCI Express switch  
- Integrated SerDes  
o Up to six configurable ports  
o 35mm x35mm, 680 pin PBGA package  
o Typical Power: 5.7 Watts  
Multi-purpose, Feature Rich ExpressLane™ PI Express Switch  
The ExpressLane PEX 8524V device offers PCI Express sng capability  
enabling users to add scalable high bandwidth, non-blockerconnection to a  
wide variety of applications including servers, storaystems, communications  
platforms, blade servers, and embedded-control oduts. The PEX 8524V is  
well suited for fan-out, aggregation, dual-grhics, eer-to-peer, and intelligent  
I/O module applications.  
ƒ PEX 8524V Key Features  
o Standard Compliant  
- PCI Express Base Specification, r1.1  
o High Performance  
- Non-blocking switch fabric  
- Full line rate on all ports  
o Non-Transparent Bridging  
- Configurable Non-Transparent port  
for Multi-Host or Intelligent I/O  
Support  
Highly Flexible Port Configurais  
The ExpressLane PEX 8524V offers hly configurable ports. There are a  
maximum of 6 ports that can be igud to any legal wdtrom x1 to x16, in any  
combination to support your spfic andwidth needs. Tports can be configured  
for symmetric (each port having e same lane widnd traffic load) or  
asymmetric (ports havindirent lane widths) the event of asymmetric  
traffic, the PEX 8524fures a flexible cenal packememory that allocates a  
memory buffer for eaport as required by the alication or endpoint. This buffer  
allocation along h the device's flexibpet flow control minimizes  
bottlenecks n the upstream and aggregated downstream bandwidths do not match  
(are asymtric)Any of the portbe designated as the upstream port, which can  
be changed dnamically.  
o Flexible Configuration  
- Six highly flexible & configurable  
ports (x1, x2, x4, x8, or x16)  
- Configurable with strapping pins,  
EEPROM, or Host software  
- Lane and polarity reversal  
o PCI Express Power Management  
- Link power management states: L0,  
L0s, L1, L2/L3 Ready, and L3  
- Device states: D0 and D3hot  
o Quality of Service (QoS)  
- Two Virtual Channels per port  
- Eight Traffic Classes per p
- Fixed and Round-Robin l  
Channel Port Arbitration  
o Reliability, Availability,  
Serviceability  
- 6 Standard Hot-Controllers  
- Upstream port as hotplug client  
- Transactioend-to-end CRC  
- Poisobit  
Ennd Packet ty  
The PEX 8524V provides to-end CRC protection (ECRC) and Poison bit  
suport to enable designs that require end-to-end data integrity. These features are  
optional in the PCI xpress specification, but PLX provides them across its entire  
ExpressLane scoduct line.  
Non-Transparent “Bridging” in a PCI Express Switch  
The EssLane PEX 8524V product supports full non-transparent bridging (NTB)  
ctiolity to allow implementation of multi-host systems and intelligent I/O  
mles in communications, storage, blade server, and graphics fan-out  
applications. To ensure quick product migration, the non-transparency features are  
mplemented in the same fashion as in standard PCI applications.  
Non-transparent bridges allow systems to isolate memory domains by presenting the  
processor subsystem as an endpoint, rather than another memory system. Base  
address registers are used to translate addresses; doorbell registers are used to send  
interrupts between the address domains; and scratchpad registers are accessible from  
both address domains to allow inter-processor communication.  
- AdvanError Reporting  
- LStatus bits and GPO ble  
- Per rt performancmong  
Average packet si
Number of packets  
CRC errors and more  
- JTAG boundary scan  
Two Virtual Channels  
The ExpressLane PEX 8524V switch supports 2 full-featured Virtual Channels  
(VCs) and a full 8 Traffic Classes (TCs). The mapping of Traffic Classes to port-  
specific Virtual Channels allows for different mappings for different ports. In  
addition, the devices offer user-selectable Virtual Channel arbitration algorithms to  
enable users to fine tune the Quality of Service (QoS) required for a specific  
application.  
Low Power with Granular SerDes Control  
The PEX 8524V provides low power capability that is fully compliant with the PCI  
Express power management specification. In addition, the SerDes physical links can  
be turned off when unused for even lower power.  

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