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PEX8548-AA25BI PDF预览

PEX8548-AA25BI

更新时间： 2024-01-28 22:41:02
品牌 Logo 应用领域
PLX 总线控制器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
4页 315K
描述
High-Performance 48-lane, 9-port PCIe Switch

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PEX8548-AA25BI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：HBGA,Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.82
地址总线宽度：总线兼容性：I2C; ISA; SPI; VGA
最大数据传输速率：312.5 MBps外部数据总线宽度：
JESD-30 代码：S-PBGA-B736JESD-609代码：e1
长度：37.5 mm湿度敏感等级：3
端子数量：736最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HBGA封装形状：SQUARE
封装形式：GRID ARRAY, HEAT SINK/SLUG峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：2.42 mm最大供电电压：1.1 V
最小供电电压：0.9 V标称供电电压：1 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：37.5 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

PEX8548-AA25BI 数据手册

 浏览型号PEX8548-AA25BI的Datasheet PDF文件第2页浏览型号PEX8548-AA25BI的Datasheet PDF文件第3页浏览型号PEX8548-AA25BI的Datasheet PDF文件第4页 
Version 1.5 2007  
PEX 8548  
Features  
ƒ PEX 8548 General Features  
o 48-lane PCI Express switch  
- Integrated SerDes  
o Up to nine configurable ports  
(x1, x2, x4, x8, x16)  
o 37.5mm x 37.5mm,  
736-ball PBGA package  
o Typical Power: 4.9 Watts  
High-Performance 48-lane, 9-port PCIe Switch  
Multi-purpose, High Performance ExpressLane™ Switch  
The ExpressLane PEX 8548 device offers PCI Express switching capability  
enabling users to add scalable high bandwidth, non-blocking interconnection  
to a wide variety of applications including servers, storage systems,  
communications platforms, blade servers, and embedded-control  
products. The PEX 8548 is well suited for fan-out, aggregation, dual-  
graphics, peer-to-peer, and fabric backplane applications.  
ƒ PEX 8548 Key Features  
o Standard Compliant  
Highly Flexible Port Configurations  
- PCI Express Base Specification, r1.1  
The PEX 8548 offers highly configurable ports. There are a maximum of 9  
ports that can be configured to any legal width from x1 to x16, in any  
combination to support your specific bandwidth needs. The ports can be  
configured for symmetric (each port having the same lane width and traffic  
load) or asymmetric (ports having different lane widths) traffic. In the event  
of asymmetric traffic, the PEX 8548 features a flexible central packet  
memory that allocates a memory buffer for each port as required by the  
application or endpoint. This buffer allocation along with the device's  
flexible packet flow control minimizes bottlenecks when the upstream and  
aggregated downstream bandwidths do not match (are asymmetric). Any of  
the ports can be designated as the upstream port, which can be changed  
dynamically.  
o High Performance  
- Non-blocking switch fabric  
- Full line rate on all ports  
- Packet Cut-Thru with 110ns max  
packet latency (x16 to x16)  
o Flexible Configuration  
- Nine highly flexible & configurable  
ports (x1, x2, x4, x8, or x16)  
- Configurable with strapping pins,  
EEPROM, I2C, or Host software  
- Lane and polarity reversal  
o PCI Express Power Management  
- Link power management states: L0,  
L0s, L1, L2/L3 Ready, and L3  
- Device states: D0 and D3hot  
o Quality of Service (QoS)  
- One Virtual Channel per port  
- Eight Traffic Classes per port  
- Weighted Round-Robin Ingress Port  
Arbitration  
High Performance  
The PEX 8548 architecture supports packet cut-thru with a max latency of  
110ns (x16 to x16). This, combined with large packet memory (1024 byte  
maximum payload size) and non-blocking internal switch architecture,  
provide full line rate on all ports for performance-hungry applications such as  
storage servers or storage switch fabrics.  
o Reliability, Availability, Serviceability  
- 3 Standard Hot-Plug Controllers  
- Upstream port as hot-plug client  
- Transaction Layer end-to-end CRC  
- Poison bit  
End-to-end Packet Integrity  
The PEX 8548 provides end-to-end CRC protection (ECRC) and Poison bit  
support to enable designs that require end-to-end data integrity. These  
features are optional in the PCI Express specification, but PLX provides  
them across its entire ExpressLane switch product line.  
- INTA# interrupt signal  
- Fatal Error (FATAL_ERR#) signal  
(legacy SERR equivalent)  
Configuration Flexibility  
The PEX 8548 provides several ways to configure its operations. The device  
can be configured through strapping pins, I2C interface, CPU configuration  
cycles, or an optional serial EEPROM. This allows for easy debug during the  
development phase, performance monitoring during the operation phase, and  
driver or software upgrade.  
- PCIe baseline error reporting  
- Advanced Error Reporting  
- Port Status bits and GPO available  
- Per port error diagnostics  
• Bad DLLPs  
• Bad TLPs  
• CRC errors  
- JTAG boundary scan  
Interoperability  
The PEX 8548 is designed to be fully compliant with the PCI Express Base  
Specification r1.1. Additionally, it supports auto-negotiation, lane reversal,  
and polarity reversal. The PEX 8548 also undergoes thorough  
interoperability testing in PLX’s Interoperability Lab.  
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