Version 0.8 2008
Features
PEX 8608 General Features
o 8-lane PCI Express switch
- Integrated 5.0 GT/s SerDes
o Up to 8 configurable ports
o 15 x 15mm2, 196-ball PBGA
o Typical Power: 1.2 Watts
PEX 8608
PEX 8608 Key Features
PCIe Gen2, 5.0 GT/s 8-lane 8-port PCI Express® Switch
o Standards Compliant
- PCI Express Base Specification r2.0
(Backwards compatible with PCIe
r1.0a/1.1)
- PCI Power Management Spec r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes Speed Control
o High Performance
- Non-blocking internal architecture
- Full line rate on all ports
- Cut-Thru latency: 130ns
- 2KB max payload size
- Read Pacing
(intelligent bandwidth allocation)
- Dual Cast
o Dual-Host & Fail-Over Support
- Configurable Non-Transparent port
- Moveable upstream port
The ExpressLane™ PEX 8608 device offers PCI Express switching capability
enabling users to add scalable high bandwidth non-blocking interconnection to a
wide variety of applications including communications platforms, control plane
applications and embedded systems. The PEX 8608 is well suited for fan-out,
aggregation, peer-to-peer, and intelligent I/O module applications.
Low Packet Latency & High Performance
The PEX 8608 architecture supports packet cut-thru with a maximum latency of
130ns in x4 to x1 configuration. This, combined with large packet memory and
non-blocking internal switch architecture, provides full line rate on all ports for low-
latency applications such as communications and embedded. The low latency
enables applications to achieve high throughput and performance. In addition to low
latency, the device supports a max payload size of 2048 bytes, enabling the user to
achieve even higher throughout.
Data Integrity
- Crosslink port capability
o Flexible Configuration
- 8 flexible & configurable ports
(x1 or x4)
The PEX 8608 provides end-to-end CRC protection (ECRC) and Poison bit support
to enable designs that require guaranteed error-free packets. PLX also supports
data path parity and memory (RAM) error correction as packets pass through the
switch.
- Configurable with strapping pins,
EEPROM, I2C, or Host software
- Lane and polarity reversal
o PCI Express Power Management
- Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
- Device states: D0 and D3hot
o Spread Spectrum Clock Isolation
- Dual clock domain
o Quality of Service (QoS)
- Two Virtual Channels (VC) per port
- Eight Traffic Classes per port
- Weighted Round-Robin Port & VC
Arbitration
Dual-Host and Fail-Over Support
The PEX 8608 supports full non-transparent bridging (NTB) functionality to allow
implementation of multi-host systems and intelligent I/O modules in applications
which require redundancy support such as communications, storage, and servers.
Non-transparent bridges allow systems to isolate host memory domains by
presenting the processor subsystem as an endpoint rather than another memory
system. Base address registers are used to translate addresses; doorbell registers are
used to send interrupts between the address domains; and scratchpad registers are
accessible from both address domains to allow inter-processor communication.
Interoperability
o Reliability, Availability, Serviceability
- All ports Hot-Plug capable thru I2C
(Hot-Plug Controller on every port)
- ECRC & Poison bit support
- Data path protection
- Memory (RAM) error correction
- Advanced Error Reporting support
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance monitoring
The PEX 8608 is designed to be fully compliant with the PCI Express Base
Specification r2.0 and is backwards compatible to PCI Express Base Specification
r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and
polarity reversal. Furthermore, the PEX 8608 is designed for Microsoft Vista
compliance. All PLX switches undergo thorough interoperability testing in PLX’s
Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure
compatibility with PCI Express devices in the market.
(per port payload & header counters)
- JTAG AC/DC boundary scan
- Fatal Error (FATAL_ERR#) output signal
- INTA# output signal
Device Operation Configuration Flexibility
The PEX 8608 provides several ways to configure its operations. The device can be
configured through strapping pins, I2C interface, CPU configuration cycles and/or an
optional serial EEPROM. This allows for easy debug during the development phase
and functional monitoring during the operation phase.
Preliminary Information Subject to Change – PLX Confidential
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