Version 1.2 2007
.
PEX 8533
Features
PEX 8533 General Features
o 32-lane PCI Express switch
- Integrated SerDes
o Up to six configurable ports
o 35mm x 35mm, 680 pin PBGA package
o Pin Compatible with PEX 8532
o Typical Power: 3.3 Watts
Flexible & Versatile PCI Express™ Switch
Multi-Purpose, Feature Rich PCI Express ExpressLane™ Switch
The ExpressLaneTM PEX 8533 device offers PCI Express switching
capability conforming to the latest revision of the PCIe Base specification.
This device enables users to add scalable high bandwidth, non-blocking
interconnects to a wide variety of applications including servers, storage
systems, communications platforms, blade servers, and embedded-control
products. The PEX 8533 is well suited for fan-out, aggregation, peer-to-
peer, backplane, and switch fabric applications.
PEX 8533 Key Features
o Standards Compliant
- PCI Express Base Specification, r1.1
- PCI SHPC Specification, r1.0
o High Performance
- Cut-through with 120ns packet latency
- Max Payload Size of 1024 Bytes
- Non-blocking switch fabric
- Full line rate on all ports
o Flexible Configuration
- Six highly flexible and configurable ports
Highly Flexible Port Configurations
The ExpressLaneTM PEX 8533 offers highly configurable ports. There are a
maximum of 6 ports that can be configured to any legal width from x1 to
x16, in any combination to support your specific bandwidth needs. The ports
can be symmetric (each port having the same lane width) or asymmetric
(ports having different lane widths). Any of the ports can be designated as
the upstream port, which can be changed dynamically.
(x1, x2, x4, x8, or x16)
- Configurable with strapping pins,
EEPROM, I2C or Host software
- Lane and polarity reversal
o PCI Express Power Management
- Link power management states: L0, L0s,
L1, L2/L3 Ready, and L3
- Device states: D0 and D3hot
o Quality of Service (QoS)
- Eight Traffic Classes per port
- Round robin and weighted RR port
arbitration
High Performance
The ExpressLaneTM PEX 8533 architecture supports packet cut-through
with a latency of 115ns (x8 to x8). This, combined with large packet
memory (256 to 1024 byte maximum payload size) and non-blocking
internal switch architecture, provide full line rate on its ports for
performance hungry applications such as storage servers or storage switch
fabrics.
o Reliability, Availability, Serviceability
- 3 Standard Hot-Plug Controllers
- Upstream port as hot-plug client
- Transaction Layer end-to-end CRC
- Poison bit
- INTA & FATAL ERROR signal support
- Advanced Error Reporting in addition to
PCIe baseline error reporting
- Port Status bits and GPO available
- Per port performance monitoring
• Average packet size, number of
packets, CRC errors
End-to-End Packet Integrity
The ExpressLaneTM PEX 8533 provides optional end-to-end CRC
protection (ECRC) and Poison bit support to enable designs that require
guaranteed error-free packets.
Configuration Flexibility
The ExpressLaneTM PEX 8533 provides several ways to configure its
operations. The device can be configured through strapping pins, I2C
interface, CPU configuration cycles, or an optional serial EEPROM. This
allows for easy debug during the development phase, performance
monitoring during the operation phase, and driver or software upgrade.
- JTAG boundary scan
Interoperability
The ExpressLaneTM PEX 8533 is designed to be fully compliant with the
PCI-SIG specification. Additionally, it supports auto-negotiation, lane
reversal, and polarity reversal. The PEX 8533 also undergoes thorough
Interoperability testing in PLX’s Interoperability Lab.
Low Power with Granular SerDes Control
The ExpressLaneTM PEX 8533 provides low power capability that is fully
compliant with the PCI Express power management specification. In
addition, the SerDes physical links can be turned off when unused for even
lower power.
PLX Confidential
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