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PEEL18CV8TI-15L

更新时间： 2024-11-28 19:45:03
品牌 Logo 应用领域
易亨 - ANACHIP 光电二极管
页数 文件大小 规格书
9页 632K
描述
EE PLD, 15ns, PAL-Type, CMOS, PDSO20,

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中文翻译

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PEEL18CV8TI-15L 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TSSOP, TSSOP20,.25Reach Compliance Code：unknown
风险等级：5.79架构：PAL-TYPE
最大时钟频率：41.6 MHzJESD-30 代码：R-PDSO-G20
输入次数：18输出次数：8
产品条款数：74端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：5 V可编程逻辑类型：EE PLD
传播延迟：15 ns认证状态：Not Qualified
子类别：Programmable Logic Devices标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

PEEL18CV8TI-15L 数据手册

 浏览型号PEEL18CV8TI-15L的Datasheet PDF文件第2页浏览型号PEEL18CV8TI-15L的Datasheet PDF文件第3页浏览型号PEEL18CV8TI-15L的Datasheet PDF文件第4页浏览型号PEEL18CV8TI-15L的Datasheet PDF文件第5页浏览型号PEEL18CV8TI-15L的Datasheet PDF文件第6页浏览型号PEEL18CV8TI-15L的Datasheet PDF文件第7页 
PEEL™ 18CV8 -7/-10/-15/-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Architectural Flexibility  
Multiple Speed Power, Temperature Options  
- Enhanced architecture fits in more logic  
- 74 product terms x 36 input AND array  
- 10 inputs and 8 I/O pins  
- VCC = 5 Volts ±10%  
- Speeds ranging from 7ns to 25 ns  
- Power as low as 37mA at 25MHz  
- Commercial and industrial versions available  
- 12 possible macrocell configurations  
- Asynchronous clear  
CMOS Electrically Erasable Technology  
- Independent output enables  
- Superior factory testing  
- 20 Pin DIP/SOIC/TSSOP and PLCC  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
Application Versatility  
Development / Programmer Support  
- Third party software and programmers  
- WinPLACE Development Software  
- PLD-to-PEEL™ JEDEC file translator  
- Replaces random logic  
- Super sets PLDs (PAL, GAL, EPLD)  
- Enhanced Architecture fits more logic than ordinary PLDs  
General Description  
The PEEL™18CV8 is a Programmable Electrically Erasable  
Logic (PEEL™) device providing an attractive alternative to  
ordinary PLDs. The PEEL™18CV8 offers the performance, flex-  
ibility, ease of design and production practicality needed by logic  
designers today.  
The PEEL™18CV8 architecture allows it to replace over 20 stan-  
dard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides addi-  
tional architecture features so more logic can be put into every  
design. Anachip’s JEDEC file translator instantly converts to the  
PEEL™18CV8 existing 20-pin PLDs without the need to rework  
the existing design. Development and programming support for the  
PEEL™18CV8 is provided by popular third-party program- mers  
and development software.  
The PEEL™18CV8 is available in 20-pin DIP, PLCC, SOIC and  
TSSOP packages with speeds ranging from 7ns to 25ns with  
power consumption as low as 37mA. EE-Reprogrammability  
provides the convenience of instant reprogramming for develop-  
ment and reusable production inventory minimizing the impact of  
programming changes or errors. EE-Reprogrammability also  
improves factory testability, thus assuring the highest quality pos-  
sible.  
Figure 3 Block Diagram  
Figure 2 Pin Configuration  
I/CLK  
1
20  
VCC  
I
I
2
3
19  
18  
17  
16  
I/O  
I/O  
I/O  
I/O  
™
I
I
4
5
I
I
6
7
15  
14  
I/O  
I/O  
I
I
8
9
13  
12  
11  
I/O  
I/O  
I
GND  
10  
TSSOP  
DIP  
SOIC  
PLCC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/9  
1234567...9

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