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PEEL18CV8ZSI-25

更新时间： 2024-11-18 22:06:27
品牌 Logo 应用领域
易亨 - ANACHIP 可编程逻辑光电二极管时钟
页数 文件大小 规格书
10页 442K
描述
CMOS Programmable Electrically Erasable Logic Device

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PEEL18CV8ZSI-25 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SOP, SOP20,.4Reach Compliance Code：unknown
风险等级：5.85Is Samacsys：N
架构：PAL-TYPE最大时钟频率：33.3 MHz
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
输入次数：18输出次数：8
产品条款数：113端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：5 V可编程逻辑类型：EE PLD
传播延迟：25 ns认证状态：Not Qualified
子类别：Programmable Logic Devices标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

PEEL18CV8ZSI-25 数据手册

 浏览型号PEEL18CV8ZSI-25的Datasheet PDF文件第2页浏览型号PEEL18CV8ZSI-25的Datasheet PDF文件第3页浏览型号PEEL18CV8ZSI-25的Datasheet PDF文件第4页浏览型号PEEL18CV8ZSI-25的Datasheet PDF文件第5页浏览型号PEEL18CV8ZSI-25的Datasheet PDF文件第6页浏览型号PEEL18CV8ZSI-25的Datasheet PDF文件第7页 
PEEL™ 18CV8Z-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Ultra Low Power Operation  
Architectural Flexibility  
- Vcc = 5 Volts ±10%  
-
-
-
-
-
-
-
-
-
Enhanced architecture fits in more logic  
113 product terms x 36 input AND array  
10 inputs and 8 I/O pins  
- Icc = 10 µA (typical) at standby  
- Icc = 2 mA (typical) at 1 MHz  
CMOS Electrically Erasable Technology  
12 possible macrocell configurations  
Asynchronous clear, Synchronous preset  
Independent output enables  
- Superior factory testing  
-
Reprogrammable in plastic package  
-
Reduces retrofit and development costs  
Programmable clock; pin 1 or p-term  
Programmable clock polarity  
Application Versatility  
-
-
-
-
Replaces random logic  
20 Pin DIP/SOIC/TSSOP and PLCC  
Super set of standard PLDs  
Pin and JEDEC compatible with 16V8  
Ideal for use in power-sensitive systems  
General Description  
The PEEL™18CV8Z is logically and functionally similar to  
Anachip’s 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z.  
The PEEL™18CV8Z is a Programmable Electrically Erasable  
Logic (PEEL™) SPLD (Simple Programmable Logic Device)  
that features ultra-low, automatic “zero” power-down operation.  
The “zero power” (100 µA max. Icc) power-down mode makes the  
PEEL™18CV8Z ideal for a broad range of battery-powered  
portable equipment applications, from hand-held meters to PCM-  
CIA modems. EE-reprogrammability provides both the conve-  
nience of fast reprogramming for product development and quick  
product personalization in manufacturing, including Engineering  
Change Orders.  
The  
differences  
between  
the  
PEEL™18CV8Z  
and  
PEEL™18CV8 include the addition of programmable clock  
polarity, a product term clock, and variable width product terms in  
the AND/OR Logic Array.  
Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset  
of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z  
provides additional architectural features that allow more logic to  
be incorporated into the design. Anachip’s JEDEC file translator  
allows easy conversion of existing 20 pin PLD designs to the  
PEEL™18CV8Z architecture without the need for redesign. The  
PEEL™18CV8Z architecture allows it to replace over twenty  
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.  
Figure 7 Pin Configuration  
I/CLK  
1
20  
VCC  
I
I
2
3
19  
18  
I/O  
I/O  
Figure 8 Block Diagram  
I
I
4
5
17  
16  
I/O  
I/O  
I
I
6
7
15  
14  
I/O  
I/O  
I
I
8
9
13  
12  
11  
I/O  
I/O  
I
CLK MUX (Optional)  
GND  
10  
™
TSSOP  
DIP  
SOIC  
PLCC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under  
any patent accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

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