5秒后页面跳转
捷配首页

Datasheet > PEEL18CV8TI-25
PEEL18CV8TI-25 PDF预览

PEEL18CV8TI-25

更新时间： 2024-11-19 20:34:55
品牌 Logo 应用领域
美台 - DIODES 时钟光电二极管可编程逻辑
页数 文件大小 规格书
9页 648K
描述
EE PLD, 25ns, PAL-Type, CMOS, PDSO20, 0.170 INCH, TSSOP-20

阅读下载

中文翻译

获取价格

PEEL18CV8TI-25 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.14
Is Samacsys：N架构：PAL-TYPE
最大时钟频率：28.5 MHzJESD-30 代码：R-PDSO-G20
JESD-609代码：e0长度：6.5 mm
专用输入次数：9I/O 线路数量：8
输入次数：18输出次数：8
产品条款数：74端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
组织：9 DEDICATED INPUTS, 8 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：245
电源：5 V可编程逻辑类型：EE PLD
传播延迟：25 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Programmable Logic Devices
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

PEEL18CV8TI-25 数据手册

 浏览型号PEEL18CV8TI-25的Datasheet PDF文件第2页浏览型号PEEL18CV8TI-25的Datasheet PDF文件第3页浏览型号PEEL18CV8TI-25的Datasheet PDF文件第4页浏览型号PEEL18CV8TI-25的Datasheet PDF文件第5页浏览型号PEEL18CV8TI-25的Datasheet PDF文件第6页浏览型号PEEL18CV8TI-25的Datasheet PDF文件第7页 
Not recommended for New designs -  
contact factory for availability  
PEEL™ 18CV8 -7/-10/-15/-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Architectural Flexibility  
Multiple Speed Power, Temperature Options  
- Enhanced architecture fits in more logic  
- 74 product terms x 36 input AND array  
- 10 inputs and 8 I/O pins  
- VCC = 5 Volts ±10%  
- Speeds ranging from 7ns to 25 ns  
- Power as low as 37mA at 25MHz  
- Commercial and industrial versions available  
- 12 possible macrocell configurations  
- Asynchronous clear  
CMOS Electrically Erasable Technology  
- Independent output enables  
- Superior factory testing  
- 20 Pin DIP/SOIC/TSSOP and PLCC  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
Application Versatility  
Development / Programmer Support  
- Third party software and programmers  
- WinPLACE Development Software  
- PLD-to-PEEL™ JEDEC file translator  
- Replaces random logic  
- Super sets PLDs (PAL, GAL, EPLD)  
- Enhanced Architecture fits more logic than ordinary PLDs  
General Description  
The PEEL™18CV8 is a Programmable Electrically Erasable  
Logic (PEEL™) device providing an attractive alternative to  
ordinary PLDs. The PEEL™18CV8 offers the performance, flex-  
ibility, ease of design and production practicality needed by logic  
designers today.  
The PEEL™18CV8 architecture allows it to replace over 20 stan-  
dard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides addi-  
tional architecture features so more logic can be put into every  
design. Anachip’s JEDEC file translator instantly converts to the  
PEEL™18CV8 existing 20-pin PLDs without the need to rework  
the existing design. Development and programming support for the  
PEEL™18CV8 is provided by popular third-party program- mers  
and development software.  
The PEEL™18CV8 is available in 20-pin DIP, PLCC, SOIC and  
TSSOP packages with speeds ranging from 7ns to 25ns with  
power consumption as low as 37mA. EE-Reprogrammability  
provides the convenience of instant reprogramming for develop-  
ment and reusable production inventory minimizing the impact of  
programming changes or errors. EE-Reprogrammability also  
improves factory testability, thus assuring the highest quality pos-  
sible.  
Figure 3 Block Diagram  
Figure 2 Pin Configuration  
I/CLK  
1
20  
VCC  
I
I
2
3
19  
18  
17  
16  
I/O  
I/O  
I/O  
I/O  
™
I
I
4
5
I
I
6
7
15  
14  
I/O  
I/O  
I
I
8
9
13  
12  
11  
I/O  
I/O  
I
GND  
10  
TSSOP  
DIP  
SOIC  
PLCC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/9  
1234567...9

中文翻译

下载PDF

与PEEL18CV8TI-25相关器件

型号 品牌 获取价格 描述 数据表
PEEL18CV8TI-25L DIODES

获取价格

 		EE PLD, 25ns, PAL-Type, CMOS, PDSO20, 0.170 INCH, LEAD FREE, TSSOP-20
PEEL18CV8TI-25L ANACHIP

获取价格

 		EE PLD, 25ns, PAL-Type, CMOS, PDSO20,
PEEL18CV8TI-5 ETC

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8TI-7 ETC

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8Z ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZJ-25 ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZJ-25L ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZJI-25 ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZJI-25L ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZP-25 ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device

与PEEL18CV8TI-25相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证