PEEL18CV8ZJI-25L

更新时间： 2024-11-18 22:07:11

品牌	Logo	应用领域
易亨 - ANACHIP		/
页数	文件大小	规格书
10页	442K
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CMOS Programmable Electrically Erasable Logic Device

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PEEL18CV8ZJI-25L 数据手册

PEEL™ 18CV8Z-25

CMOS Programmable Electrically Erasable Logic Device

Features

Ultra Low Power Operation

Architectural Flexibility

- Vcc = 5 Volts ±10%

Enhanced architecture fits in more logic

113 product terms x 36 input AND array

10 inputs and 8 I/O pins

- Icc = 10 µA (typical) at standby

- Icc = 2 mA (typical) at 1 MHz

CMOS Electrically Erasable Technology

12 possible macrocell configurations

Asynchronous clear, Synchronous preset

Independent output enables

- Superior factory testing

Reprogrammable in plastic package

Reduces retrofit and development costs

Programmable clock; pin 1 or p-term

Programmable clock polarity

Application Versatility

Replaces random logic

20 Pin DIP/SOIC/TSSOP and PLCC

Super set of standard PLDs

Pin and JEDEC compatible with 16V8

Ideal for use in power-sensitive systems

General Description

The PEEL™18CV8Z is logically and functionally similar to

Anachip’s 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z.

The PEEL™18CV8Z is a Programmable Electrically Erasable

Logic (PEEL™) SPLD (Simple Programmable Logic Device)

that features ultra-low, automatic “zero” power-down operation.

The “zero power” (100 µA max. Icc) power-down mode makes the

PEEL™18CV8Z ideal for a broad range of battery-powered

portable equipment applications, from hand-held meters to PCM-

CIA modems. EE-reprogrammability provides both the conve-

nience of fast reprogramming for product development and quick

product personalization in manufacturing, including Engineering

Change Orders.

The

differences

between

the

PEEL™18CV8Z

and

PEEL™18CV8 include the addition of programmable clock

polarity, a product term clock, and variable width product terms in

the AND/OR Logic Array.

Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset

of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z

provides additional architectural features that allow more logic to

be incorporated into the design. Anachip’s JEDEC file translator

allows easy conversion of existing 20 pin PLD designs to the

PEEL™18CV8Z architecture without the need for redesign. The

PEEL™18CV8Z architecture allows it to replace over twenty

standard 20-pin DIP, SOIC, TSSOP and PLCC packages.

Figure 7 Pin Configuration

I/CLK

VCC

I/O

Figure 8 Block Diagram

I/O

CLK MUX (Optional)

GND

™

TSSOP

DIP

SOIC

PLCC

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under

any patent accompany the sale of the product.

Rev. 1.0 Dec 16, 2004

1/10

12 3 4 5 6 7...10

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与PEEL18CV8ZJI-25L相关器件

型号	品牌	获取价格	描述	数据表
PEEL18CV8ZP-25	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZP-25L	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZPI-25	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZPI-25L	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZS-25	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZS-25L	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZSI-25	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZSI-25L	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZT-25	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device
PEEL18CV8ZT-25L	ANACHIP	获取价格	CMOS Programmable Electrically Erasable Logic Device

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