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PDM41258LA12SO PDF预览

PDM41258LA12SO

更新时间: 2024-09-19 20:34:55
品牌 Logo 应用领域
IXYS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 276K
描述
Standard SRAM, 64KX4, 12ns, CMOS, PDSO24

PDM41258LA12SO 技术参数

生命周期:Obsolete包装说明:SOJ, SOJ24,.34
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J24内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
端子数量:24字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX4输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ24,.34封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
最大待机电流:0.0005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.16 mA
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

PDM41258LA12SO 数据手册

 浏览型号PDM41258LA12SO的Datasheet PDF文件第2页浏览型号PDM41258LA12SO的Datasheet PDF文件第3页浏览型号PDM41258LA12SO的Datasheet PDF文件第4页浏览型号PDM41258LA12SO的Datasheet PDF文件第5页浏览型号PDM41258LA12SO的Datasheet PDF文件第6页浏览型号PDM41258LA12SO的Datasheet PDF文件第7页 
PDM41258  
256K Static RAM  
64K x 4-Bit  
1
2
Description  
Features  
The PDM41258 is a high-performance CMOS static  
RAM organized as 65,536 x 4 bits. Writing to this  
device is accomplished when the write enable (WE)  
and the chip enable (CE) inputs are both LOW.  
Reading is accomplished when WE remains HIGH  
and CE goes LOW.  
High speed access times  
Com’l: 7, 8, 10, 12 and 15 ns  
Ind’l: 8, 10, 12 and 15 ns  
Low power operation (typical)  
- PDM41258SA  
Active: 400 mW  
Standby: 150 mW  
- PDM41258LA  
Active: 350 mW  
Standby: 25 mW  
The PDM41258 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL-  
compatible. The PDM41258 comes in two versions,  
the standard power version PDM41258SA and a low  
power version the PDM41258LA. The two versions  
are functionally the same and only differ in their  
power consumption.  
4
Single +5V (±10%) power supply  
TTL compatible inputs and outputs  
Packages  
5
The PDM41258 is available in a 24-pin 300-mil plas-  
tic SOJ for surface mount applications.  
Plastic SOJ (300 mil) - SO  
6
Functional Block Diagram  
7
A0  
Decoder  
Memory  
Matrix  
8
Addresses  
A15  
9
• • • • •  
I/O0  
I/O1  
I/O2  
I/O3  
Input  
Data  
Control  
Column I/O  
10  
11  
12  
CE  
WE  
Rev. 2.2 - 4/27/98  
1

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