Datasheet > PDM41258LA15SOITR

PDM41258LA15SOITR

更新时间： 2024-09-19 15:47:39

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
8页	276K
描述
SRAM

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技术参数
数据手册

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PDM41258LA15SOITR 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.84
Base Number Matches：	1

PDM41258LA15SOITR 数据手册

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PDM41258

256K Static RAM

64K x 4-Bit

Description

Features

The PDM41258 is a high-performance CMOS static

RAM organized as 65,536 x 4 bits. Writing to this

device is accomplished when the write enable (WE)

and the chip enable (CE) inputs are both LOW.

Reading is accomplished when WE remains HIGH

and CE goes LOW.

■ High speed access times

Com’l: 7, 8, 10, 12 and 15 ns

Ind’l: 8, 10, 12 and 15 ns

■ Low power operation (typical)

- PDM41258SA

Active: 400 mW

Standby: 150 mW

- PDM41258LA

Active: 350 mW

Standby: 25 mW

The PDM41258 operates from a single +5V power

supply and all the inputs and outputs are fully TTL-

compatible. The PDM41258 comes in two versions,

the standard power version PDM41258SA and a low

power version the PDM41258LA. The two versions

are functionally the same and only differ in their

power consumption.

■ Single +5V (±10%) power supply

■ TTL compatible inputs and outputs

■ Packages

The PDM41258 is available in a 24-pin 300-mil plas-

tic SOJ for surface mount applications.

Plastic SOJ (300 mil) - SO

Functional Block Diagram

A₀

Decoder

Memory

Matrix

•

Addresses

•

A₁₅

• • • • •

I/O₀

I/O₁

I/O₂

I/O₃

Input

Data

Control

Column I/O

Rev. 2.2 - 4/27/98

12 3 4 5 6 7 8

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