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PCA9654EADR2G

更新时间： 2024-11-14 19:36:55
品牌 Logo 应用领域
安森美 - ONSEMI 接口集成电路
页数 文件大小 规格书
22页 317K
描述
IC SPECIALTY INTERFACE CIRCUIT, Interface IC:Other

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中文翻译

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PCA9654EADR2G 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：,Reach Compliance Code：compliant
风险等级：5.59接口集成电路类型：INTERFACE CIRCUIT
Base Number Matches：1

PCA9654EADR2G 数据手册

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PCA9654E, PCA9654EA  
8-bit I/O Expander for I2C  
Bus and SMBus with  
Interrupt  
The PCA9654E/PCA9654EA provides 8 bits of General Purpose  
2
parallel Input/Output (GPIO) expansion for I C−bus/SMBus  
applications.  
http://onsemi.com  
MARKING  
The PCA9654E/PCA9654EA consists of 8−bit Configuration  
(Input or Output selection); Input, Output and Polarity Inversion  
(active HIGH or active LOW operation) registers. The system master  
may set the I/Os as either inputs or outputs by writing to the I/O  
configuration bits. The data for each Input or Output is kept in the  
corresponding Input or Output register. The polarity of the read  
register can be inverted with the Polarity Inversion register. All  
registers can be read by the system master.  
DIAGRAMS  
16  
1
1
PCA9654E  
AWLYWWG  
SOIC−16  
D SUFFIX  
CASE 751B  
The PCA9654E/PCA9654EA open−drain interrupt (INT) output is  
activated when any input state differs from its corresponding input  
port register state and is used to indicate to the system master that an  
input state has changed. The power−on reset sets the registers to their  
default values and initializes the device state machine.  
16  
PCA9  
654E  
ALYWG  
G
1
TSSOP−16  
DT SUFFIX  
CASE 948F  
2
1
1
Three hardware pins (AD0, AD1, AD2) vary the fixed I C bus  
2
address and allow up to 64 devices to share the same I C−bus/SMBus.  
16  
The PCA9654EA has a different address map from the PCA9654E.  
Features  
XXMG  
1
• V Operating Range: 1.65 V to 5.5 V  
DD  
G
WQFN16  
MT SUFFIX  
CASE 488AP  
• SDA Sink Capability: 30 mA  
• 5.5 V Tolerant I/Os  
• Polarity Inversion Register  
16  
• Active LOW Interrupt Output  
• Low Standby Current  
1
1
XXXX  
XXXX  
ALYWG  
G
1
QFN16 3x3  
MN SUFFIX  
CASE 485G  
• Noise Filter on SCL/SDA Inputs  
• No Glitch on Power−up  
• Internal Power−on Reset  
16  
• 64 Programmable Slave Addresses Using 3 Address Pins  
• 8 I/O Pins which Default to 8 Inputs  
XXXXXX  
XXXXXX  
ALYWG  
G
1
2
QFN16 4x4  
MN SUFFIX  
CASE 485AP  
• I C SCL Clock Frequencies Supported:  
Standard Mode: 100 kHz  
Fast Mode: 400 kHz  
Fast Mode +: 1 MHz  
XXXX = Specific Device Code  
A
M
= Assembly Location  
• ESD Performance: 4000 V Human Body Model,  
400 V Machine Model  
= Date Code / Assembly Location  
WL, L = Wafer Lot  
= Year  
WW, W = Work Week  
Y
• These are Pb−Free Devices  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 17 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
May, 2014 − Rev. 1  
PCA9654E/D  
1234567...22

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