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PCA9661B,118 PDF预览

PCA9661B,118

更新时间： 2024-11-14 18:45:35
品牌 Logo 应用领域
恩智浦 - NXP 时钟PC驱动外围集成电路驱动器
页数 文件大小 规格书
63页 1079K
描述
PCA9661 - Parallel bus to 1 channel Fm+ I2C-bus controller QFP 48-Pin

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PCA9661B,118 技术参数

Source Url Status Check Date：2013-06-14 00:00:00是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP48,.35SQ,20针数：48
Reach Compliance Code：compliant风险等级：5.77
地址总线宽度：8总线兼容性：I2C
最大时钟频率：12 MHz驱动器接口标准：IEEE 1149.1
外部数据总线宽度：8JESD-30 代码：S-PQFP-G48
JESD-609代码：e3长度：7 mm
湿度敏感等级：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Bus Controllers
最大压摆率：25 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, I2C
Base Number Matches：1

PCA9661B,118 数据手册

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PCA9661  
Parallel bus to 1 channel Fm+ I2C-bus controller  
Rev. 1 — 4 August 2011  
Product data sheet  
1. General description  
The PCA9661 is an advanced single master mode I2C-bus controller. It is a fourth  
generation bus controller designed for data intensive I2C-bus data transfers. It has one  
I2C-bus channel with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+)  
open-drain topology. The serial channel has a generous 4352 byte data buffer which  
makes the PCA9661 the ideal companion to any CPU that needs to transmit and receive  
large amounts of serial data with minimal interruptions.  
The PCA9661 is a 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to  
communicate with up to 64 slaves in one serial sequence with no intervention from the  
CPU. The controller also has a sequence loop control feature that allows it to  
automatically retransmit a stored sequence.  
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus  
and for the interval timer used in sequence looping. This feature greatly reduces CPU  
overhead when data refresh is required in fault tolerant applications.  
An external trigger input allows data synchronization with external events. The trigger  
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.  
Error reporting is handled at the transaction level, channel level, and controller level.  
A simple interrupt tree and interrupt masks allow further customization of interrupt  
management.  
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are  
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.  
2. Features and benefits  
Parallel-bus to I2C-bus protocol converter and interface  
1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability  
Internal oscillator trimmed to 1 % accuracy reduces external components  
4352-byte buffer for the Fm+ channel  
Three levels of reset: individual software channel reset, global software reset, global  
hardware RESET pin  
Communicates with up to 64 slaves in one serial sequence  
Sequence looping with interval timer  
Supports SCL clock stretching  
JTAG port available for boundary scan testing during board manufacturing process  
Trigger input synchronizes serial communication exactly with external events  
Maskable interrupts  
 
 
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