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PCA9655EDTR2G PDF预览

PCA9655EDTR2G

更新时间： 2024-11-14 12:49:07
品牌 Logo 应用领域
安森美 - ONSEMI 驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
20页 215K
描述
Remote 16-bit I/O Expander for I2C Bus with Interrupt

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中文翻译

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PCA9655EDTR2G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：TSSOP包装说明：TSSOP-24
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：15 weeks
风险等级：2.01接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm湿度敏感等级：1
功能数量：1端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：5.5 V
最小供电电压：1.65 V标称供电电压：2.3 V
表面贴装：YES温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

PCA9655EDTR2G 数据手册

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PCA9655E  
Remote 16-bit I/O Expander  
for I2C Bus with Interrupt  
The PCA9655E provides 16 bits of General Purpose parallel Input /  
2
Output (GPIO) expansion through the I C−bus / SMBus.  
The PCA9655E consists of two 8−bit Configuration (Input or  
Output selection); Input, Output and Polarity Inversion (active−HIGH  
or active−LOW operation) registers. At power on, all I/Os default to  
inputs. Each I/O may be configured as either input or output by writing  
to its corresponding I/O configuration bit. The data for each Input or  
Output is kept in its corresponding Input or Output register. The  
Polarity Inversion register may be used to invert the polarity of the  
read register. All registers can be read by the system master.  
The PCA9655E provides an open−drain interrupt output which is  
activated when any input state differs from its corresponding input  
port register state. The interrupt output is used to indicate to the system  
master that an input state has changed. The power−on reset sets the  
registers to their default values and initializes the device state  
machine.  
http://onsemi.com  
MARKING  
DIAGRAMS  
PCA9655E  
AWLYYWWG  
SOIC−24  
DW SUFFIX  
CASE 751E  
PCA96  
55EG  
Three hardware pins (AD0, AD1, AD2) are used to configure the  
2
I C−bus slave address of the device. Up to 64 devices are allowed to  
AWLYYWW  
TSSOP−24  
DT SUFFIX  
CASE 948H  
2
share the same I C−bus / SMBus.  
Features  
• V Operating Range: 1.65 V to 5.5 V  
DD  
• SDA Sink Capability: 30 mA  
• 5.5 V Tolerant I/Os  
PCA  
9655E  
ALYWG  
G
1
WQFN24  
MT SUFFIX  
CASE 485BG  
• Polarity Inversion Register  
• Active LOW Interrupt Output  
• Low Standby Current  
• Noise Filter on SCL/SDA Inputs  
• No Glitch on Power−up  
XXXX = Specific Device Code  
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
A
• Internal Power−on Reset  
• 64 Programmable Slave Addresses Using Three Address Pins  
• 16 I/O Pins Which Default to 16 Inputs  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
2
• I C SCL Clock Frequencies Supported:  
Standard Mode: 100 kHz  
Fast Mode: 400 kHz  
Fast Mode +: 1 MHz  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 17 of this data sheet.  
• ESD Performance: 2000 V Human Body Model,  
200 V Machine Model  
• These are Pb−Free Devices  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
May, 2012 − Rev. 1  
PCA9655E/D  
1234567...20

中文翻译

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