8.0 Registers (Continued)
B. The transmitter FIFO empty indications will be delayed 1
character time minus the last stop bit time whenever the
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following occurs: THRE 1 and there have not been at
least two bytes at the same time in the transmit FIFO,
Bit 7: This bit is the complement of the Data Carrier Detect
(DCD) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to OUT 2 in the MCR.
8.10 SCRATCHPAD REGISTER
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since the last THRE 1. The first transmitter interrupt af-
ter changing FCR0 will be immediate, if it is enabled.
This 8-bit Read/Write Register does not control the UART
in anyway. It is intended as a scratchpad register to be used
by the programmer to hold data temporarily.
Character timeout and RCVR FIFO trigger level interrupts
have the same priority as the current received data avail-
able interrupt; XMIT FIFO empty has the same priority as
the current transmitter holding register empty interrupt.
8.11 FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are enabled
e
e
(FCR0 1, IER0 1) RCVR interrupts will occur as follows:
8.12 FIFO POLLED MODE OPERATION
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A. The receive data available interrupt will be issued to the
CPU when the FIFO has reached its programmed trigger
level; it will be cleared as soon as the FIFO drops below
its programmed trigger level.
With FCR0 1 resetting IER0, IER1, IER2, IER3 or all to
zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately
either one or both can be in the polled mode of operation.
B. The IIR receive data available indication also occurs
when the FIFO trigger level is reached, and like the inter-
rupt it is cleared when the FIFO drops below the trigger
level.
In this mode the user’s program will check RCVR and XMIT-
TER status via the LSR. As stated previously:
LSR0 will be set as long as there is one byte in the RCVR
FIFO.
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C. The receiver line status interrupt (IIR 06), as before,
has higher priority than the received data available
e
(IIR 04) interrupt.
LSR1 to LSR4 will specify which error(s) has occurred.
Character error status is handled the same way as when
in the interrupt mode, the IIR is not affected since
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IER2 0.
D. The data ready bit (LSR0) is set as soon as a character is
transferred from the shift register to the RCVR FIFO. It is
reset when the FIFO is empty.
LSR5 will indicate when the XMIT FIFO is empty.
LSR6 will indicate that both the XMIT FIFO and shift reg-
ister are empty.
When RCVR FIFO and receiver interrupts are enabled,
RCVR FIFO timeout interrupts will occur as follows:
LSR7 will indicate whether there are any errors in the
RCVR FIFO.
A. A FIFO timeout interrupt will occur, if the following condi-
tions exist:
There is no trigger level reached or timeout condition indi-
cated in the FIFO Polled Mode, however, the RCVR and
XMIT FIFOs are still fully capable of holding characters.
Ð at least one character is in the FIFO
Ð the most recent serial character received was
longer than 4 continuous character times ago (if 2
stop bits are programmed the second one is in-
cluded in this time delay).
9.0 Typical Applications
Typical Interface for a
High-Capacity Data Bus
Ð the most recent CPU read of the FIFO was longer
than 4 continuous character times ago.
The maximum time between a received character and a
timeout interrupt will be 160 ms at 300 baud with a 12-bit
receive character (i.e., 1 Start, 8 Data, 1 Parity and 2 Stop
Bits).
B. Character times are calculated by using the RCLK input
for a clock signal (this makes the delay proportional to
the baudrate).
C. When a timeout interrupt has occurred it is cleared and
the timer reset when the CPU reads one character from
the RCVR FIFO.
TL/C/8652–23
D. When a timeout interrupt has not occurred the timeout
timer is reset after a new character is received or after
the CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled
e
e
(FCR0 1, IER1 1), XMIT interrupts will occur as follows:
A. The transmitter holding register interrupt (02) occurs
when the XMIT FIFO is empty; it is cleared as soon as
the transmitter holding register is written to (1 to 16 char-
acters may be written to the XMIT FIFO while servicing
this interrupt) or the IIR is read.
19
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