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PC16552D

更新时间： 2024-11-17 22:44:31

品牌	Logo	应用领域
美国国家半导体 - NSC		先进先出芯片
页数	文件大小	规格书
21页	293K
描述
Dual Universal Asynchronous Receiver/Transmitter with FIFOs

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PC16552D 数据手册

June 1995

PC16552D

Dual Universal Asynchronous

Receiver/Transmitter with FIFOs

General Description

Features

Dual independent UARTs

The PC16552D is a dual version of the PC16550D Universal

Asynchronous Receiver/Transmitter (UART). The two serial

channels are completely independent except for a common

CPU interface and crystal input. On power-up both channels

are functionally identical to the 16450*. Each channel can

operate with on-chip transmitter and receiver FIFOs (FIFO

mode) to relieve the CPU of excessive software overhead.

In FIFO mode each channel is capable of buffering 16 bytes

(plus 3 bits of error data per byte in the RCVR FIFO) of data

in both the transmitter and receiver. All the FIFO control

logic is on-chip to minimize system overhead and maximize

system efficiency.

Capable of running all existing 16450 and PC16550D

software

After reset, all registers are identical to the 16450 reg-

ister set

Read and write cycle times of 84 ns

In the FIFO mode transmitter and receiver are each

buffered with 16-byte FIFOs to reduce the number of

interrupts presented to the CPU

Holding and shift registers in the 16450 Mode eliminate

the need for precise synchronization between the CPU

and serial data

Signalling for DMA transfers is done through two pins per

channel (TXRDY and RXRDY). The RXRDY function is mul-

tiplexed on one pin with the OUT 2 and BAUDOUT func-

tions. The CPU can select these functions through a new

Adds or deletes standard asynchronous communication

bits (start, stop, and parity) to or from the serial data

Independently controlled transmit, receive, line status,

and data set interrupts

Programmable baud generators divide any input clock

Each channel performs serial-to-parallel conversion on data

characters received from a peripheral device or a MODEM,

and parallel-to-serial conversion on data characters re-

ceived from the CPU. The CPU can read the complete

status of each channel at any time. Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the DUART, as well as any error

conditions (parity, overrun, framing, or break interrupt).

clock

by 1 to (2

1) and generate the 16

MODEM control functions (CTS, RTS, DSR, DTR, RI,

and DCD)

Fully programmable serial-interface characteristics:

Ð 5-, 6-, 7-, or 8-bit characters

Ð Even, odd, or no-parity bit generation and detection

Ð 1-, 1(/2-, or 2-stop bit generation

Ð Baud generation (DC to 1.5M baud) with 16

False start bit detection

clock

The DUART includes one programmable baud rate genera-

tor for each channel. Each is capable of dividing the clock

Complete status reporting capabilities

1), and producing a 16

clock for driving the internal transmitter logic. Provisions are

input by divisors of 1 to (2

TRI-STATE TTL drive for the data and control buses

Line break generation and detection

also included to use this 16

clock to drive the receiver

Internal diagnostic capabilities:

Ð Loopback controls for communications link fault

isolation

Ð Break, parity, overrun, framing error simulation

Full prioritized interrupt system controls

logic. The DUART has complete MODEM-control capability,

and a processor-interrupt system. Interrupts can be pro-

grammed to the user’s requirements, minimizing the com-

puting required to handle the communications link.

The DUART is fabricated using National Semiconductor’s

advanced M CMOS^TM

*Can also be reset to 16450 Mode under software control.

Note: This part is patented.

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation

CMOS^TMis a trademark of National Semiconductor Corporation

1995 National Semiconductor Corporation

TL/C/9426

RRD-B30M75/Printed in U. S. A.

12 3 4 5 6 7...21

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与PC16552D相关器件

型号	品牌	获取价格	描述	数据表
PC16552DV	NSC	获取价格	Dual Universal Asynchronous Receiver/Transmitter with FIFOs
PC16552DV/NOPB	NSC	获取价格	IC 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44
PC16552DVX	ETC	获取价格	UART
PC16552DVX/NOPB	NSC	获取价格	IC 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44
PC16553	NSC	获取价格	Dual Universal Asynchronous Receiver/Transmitter with FIFOs plus High Performance Parallel
PC16553V	NSC	获取价格	Dual Universal Asynchronous Receiver/Transmitter with FIFOs plus High Performance Parallel
PC16553V/A+	ETC	获取价格	UART
PC-16-55B55	PULSE	获取价格	Low Frequency, Open-Style Laminated, Concentric Vertical Profile, PC Plug-In Series
PC-1660(10)	HRS	获取价格	连接器类型:其他;线束品:无;盐水喷雾时间(耐腐蚀性):h;PIN数:60;开口间距:2.
PC-16-640	PULSE	获取价格	Signals PC low power transformers are designed to operate between 50 Hz and 500 Hz without

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