Datasheet > PC16550DV/NOPB

PC16550DV/NOPB

更新时间： 2024-01-08 13:15:54

品牌	Logo	应用领域
美国国家半导体 - NSC		通信时钟数据传输外围集成电路
页数	文件大小	规格书
22页	342K
描述
IC 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44, PLASTIC, LCC-44, Serial IO/Communication Controller

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PC16550DV/NOPB 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	QCCJ, LDCC44,.7SQ	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.2	地址总线宽度：	3
边界扫描：	NO	总线兼容性：	8088
最大时钟频率：	24 MHz	通信协议：	ASYNC, BIT
数据编码/解码方法：	NRZ	最大数据传输速率：	0.1875 MBps
外部数据总线宽度：	8	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e3	长度：	16.51 mm
低功率模式：	NO	湿度敏感等级：	3
DMA 通道数量：		I/O 线路数量：
串行 I/O 数：	1	端子数量：	44
片上数据RAM宽度：		最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	245	电源：	5 V
认证状态：	Not Qualified	RAM（字数）：	0
座面最大高度：	4.57 mm	子类别：	Serial IO/Communication Controllers
最大压摆率：	15 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	16.51 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：	1

PC16550DV/NOPB 数据手册

June 1995

PC16550D Universal Asynchronous

Receiver/Transmitter with FIFOs

General Description

Features

Capable of running all existing 16450 software.

Pin for pin compatible with the existing 16450 except

for CSOUT (24) and NC (29). The former CSOUT and

NC pins are TXRDY and RXRDY, respectively.

After reset, all registers are identical to the 16450 reg-

ister set.

The PC16550D is an improved version of the original 16450

Universal Asynchronous Receiver/Transmitter (UART).

Functionally identical to the 16450 on powerup (CHARAC-

TER mode)* the PC16550D can be put into an alternate

mode (FIFO mode) to relieve the CPU of excessive software

overhead.

In this mode internal FIFOs are activated allowing 16 bytes

(plus 3 bits of error data per byte in the RCVR FIFO) to be

stored in both receive and transmit modes. All the logic is on

chip to minimize system overhead and maximize system ef-

ficiency. Two pin functions have been changed to allow sig-

nalling of DMA transfers.

In the FIFO mode transmitter and receiver are each

buffered with 16 byte FIFO’s to reduce the number of

interrrupts presented to the CPU.

Adds or deletes standard asynchronous communication

bits (start, stop, and parity) to or from the serial data.

Holding and shift registers in the 16450 Mode eliminate

the need for precise synchronization between the CPU

and serial data.

The UART performs serial-to-parallel conversion on data

characters received from a peripheral device or a MODEM,

and parallel-to-serial conversion on data characters re-

ceived from the CPU. The CPU can read the complete

status of the UART at any time during the functional opera-

tion. Status information reported includes the type and con-

dition of the transfer operations being performed by the

UART, as well as any error conditions (parity, overrun, fram-

ing, or break interrupt).

Independently controlled transmit, receive, line status,

and data set interrupts.

Programmable baud generator divides any input clock

Independent receiver clock input.

clock.

by 1 to (2

1) and generates the 16

MODEM control functions (CTS, RTS, DSR, DTR, RI,

and DCD).

The UART includes a programmable baud rate generator

that is capable of dividing the timing reference clock input

Fully programmable serial-interface characteristics:

Ð 5-, 6-, 7-, or 8-bit characters

Ð Even, odd, or no-parity bit generation and detection

Ð 1-, 1(/2-, or 2-stop bit generation

Ð Baud generation (DC to 1.5M baud).

False start bit detection.

clock for

driving the internal transmitter logic. Provisions are also in-

by divisors of 1 to (2

1), and producing a 16

cluded to use this 16 clock to drive the receiver logic. The

UART has complete MODEM-control capability, and a proc-

essor-interrupt system. Interrupts can be programmed to

the user’s requirements, minimizing the computing required

to handle the communications link.

Complete status reporting capabilities.

TRI-STATE TTL drive for the data and control buses.

Line break generation and detection.

The UART is fabricated using National Semiconductor’s ad-

vanced M CMOS process.

Internal diagnostic capabilities:

Ð Loopback controls for communications link fault

isolation

*Can also be reset to 16450 Mode under software control.

Ð Break, parity, overrun, framing error simulation.

Full prioritized interrupt system controls.

Note: This part is patented.

Basic Configuration

TL/C/8652–1

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation

TL/C/8652

RRD-B30M75/Printed in U. S. A.

12 3 4 5 6 7...22

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