FINAL
COM’L: H-25
PALCE29MA16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
■ High-performance semicustom logic
replacement; Electrically Erasable (EE)
technology allows reprogrammability
■ Register/Latch Preload permits full logic
verification
■ High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX
■ 16 bidirectional user-programmable I/O logic
macrocells for Combinatorial/Registered/
Latched operation
internal = 50 MHz)
■ Full-function AC and DC testing at the factory
for high programming and functional yields
and high reliability
■ Output Enable controlled by a pin or product
terms
■ 24-pin 300 mil SKINNYDIP and 28-pin plastic
■ Varied product term distribution for increased
leaded chip carrier packages
design flexibility
■ Extensive third-party software and programmer
■ Programmable clock selection with common
pin clock/latch enable (LE) or individual
product term clock/LE with LOW/HIGH clock/
LE polarity
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Pro-
grammable Array Logic (PAL) device designed for gen-
eral logic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high
programming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other
BLOCK DIAGRAM
I/O
I/O
I/O
I/OF
I/OF
I/O
I/O
I/OF
I/OF
4
7
6
6
5
4
5
CLK/LE
7
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
Logic
Macrocell
4
4
4
4
4
4
4
4
4
4
8
12
12
8
4
4
Programmable
AND Array
58x178
4
4
12
8
8
4
12
4
4
4
4
4
4
4
4
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
4
I/O
1
I/OF
0
I/OF
1
I/O
0
I/O
2
I/OF
3
I
-I
I/O
3
I/OF
2
I/OE
3
0
08811G-1
Publication# 08811 Rev. G Amendment/0
Issue Date: June 1993
2-349