Datasheet > PALCE26V12H-20JI/4

PALCE26V12H-20JI/4

更新时间： 2024-11-08 20:24:51

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟输入元件可编程逻辑
页数	文件大小	规格书
20页	195K
描述
EE PLD, 20ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

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技术参数
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PALCE26V12H-20JI/4 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, LCC-28	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.8	架构：	PAL-TYPE
最大时钟频率：	40 MHz	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.5062 mm
湿度敏感等级：	1	专用输入次数：	12
I/O 线路数量：	12	输入次数：	26
输出次数：	12	产品条款数：	136
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	12 DEDICATED INPUTS, 12 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	20 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.5062 mm	Base Number Matches：	1

PALCE26V12H-20JI/4 数据手册

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USE GAL DEVICES FOR NEW DESIGNS

FINAL

COM’L: H-7/10/15/20

IND: H-10/15/20

Lattice Semiconductor

PALCE26V12 Family

28-Pin EE CMOS Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

■ 28-pin versatile PAL programmable logic

■ Two clock inputs for independent functions

device architecture

■ Global asynchronous reset and synchronous

■ Electrically erasable CMOS technology

provides half power (only 115 mA) at high

speed (7.5 ns propagation delay)

preset for initialization

■ Register preload for testability and built-in

■ 14 dedicated inputs and 12 input/output

■ Space-efficient 28-pin SKINNYDIP and PLCC

macrocells for architectural flexibility

packages

■ Macrocells can be registered or combinatorial,

■ Center VCC and GND pins to improve signal

and active high or active low

characteristics

■ Varied product term distribution allows up to

■ Extensive third-party software and programmer

16 product terms per output

support through FusionPLD partners

GENERAL DESCRIPTION

The PALCE26V12 is a 28-pin version of the popular

PAL22V10 architecture. Built with low-power, high-

speed, electrically-erasable CMOS technology, the

PALCE26V12 offers many unique advantages.

The product terms are connected to the fixed OR array

with a varied distribution from 8 to 16 across the outputs

(see Block Diagram). The OR sum of the products feeds

the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial, active high or

active low, with registered I/O possible. The flip-flop can

be clocked by one of two clock inputs. The output

configuration is determined by four bits controlling three

multiplexers in each macrocell.

Device logic is automatically configured according to

the user’s design specification. Design is simplified by

design software, allowing automatic creation of a

programming file based on Boolean or state equations.

The software can also be used to verify the design and

can provide test vectors for the programmed device.

The PALCE26V12 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced

to sum-of-products form, taking advantage of the

very wide input gates available in PAL devices. The

functions are programmed into the device through

electrically-erasable floating-gate cells in the AND logic

array and the macrocells. In the unprogrammed state,

all AND product terms float HIGH. If both true and

complement of any input are connected, the term will be

permanently LOW.

Publication# 16072 Rev. E Amendment/0

Issue Date: February 1996

2-306

12 3 4 5 6 7...20

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与PALCE26V12H-20JI/4相关器件

型号	品牌	获取价格	描述	数据表
PALCE26V12H-20PC	AMD	获取价格	28-Pin EE CMOS Versatile PAL Device
PALCE26V12H-20PC/4	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28
PALCE26V12H-20PI	AMD	获取价格	28-Pin EE CMOS Versatile PAL Device
PALCE26V12H-20PI/4	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28
PALCE26V12H-25JC	ETC	获取价格	Electrically-Erasable PLD
PALCE26V12H-25PC	ETC	获取价格	Electrically-Erasable PLD
PALCE26V12H-7	AMD	获取价格	28-Pin EE CMOS Versatile PAL Device
PALCE26V12H-7JC	AMD	获取价格	28-Pin EE CMOS Versatile PAL Device
PALCE26V12H-7JC/4	LATTICE	获取价格	EE PLD, 7.5ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
PALCE26V12H-7JC/5	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQCC28,

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