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PALCE29M16H-25 PDF预览

PALCE29M16H-25

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超微 - AMD /
页数 文件大小 规格书
22页 302K
描述
24-Pin EE CMOS Programmable Array Logic

PALCE29M16H-25 数据手册

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FINAL  
COM’L: H-25  
Advanced  
Micro  
PALCE29M16H-25  
24-Pin EE CMOS Programmable Array Logic  
Devices  
DISTINCTIVE CHARACTERISTICS  
High-performance semicustom logic  
replacement; Electrically Erasable (EE)  
technology allows reprogrammability  
Register/Latch Preload permits full logic  
verification  
High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX  
16 bidirectional user-programmable I/O logic  
macrocells for Combinatorial/Registered/  
Latched operation  
internal = 50 MHz)  
Full-function AC and DC testing at the factory  
for high programming and functional yields  
and high reliability  
Output Enable controlled by a pin or product  
terms  
24-Pin 300 mil SKINNYDIP and 28-pin plastic  
Varied product term distribution for increased  
leaded chip carrier packages  
design flexibility  
Extensive third-party software and programmer  
Programmable clock selection with two clocks/  
latch enables (LEs) and LOW/HIGH clock/LE  
polarity  
support through FusionPLD partners  
GENERAL DESCRIPTION  
The PALCE29M16 is a high-speed, EE CMOS Pro-  
grammable Array Logic (PAL) device designed for gen-  
eral logic replacement in TTL or CMOS digital systems.  
It offers high speed, low power consumption, high pro-  
gramming yield, fast programming and excellent reli-  
ability. PAL devices combine the flexibility of custom  
logic with the off-the-shelf availability of standard prod-  
ucts, providing major advantages over other semicus-  
tom solutions such as gate arrays and standard cells,  
including reduced development time and low up-front  
development cost.  
BLOCK DIAGRAM  
I/O  
I/O  
I/O  
I/OF  
I/OF  
I/O  
I/O  
I/OF  
I/OF  
4
4
6
6
5
5
CLK/LE  
7
7
I/CLK/LE  
OE  
PTs  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Macrocell  
Macrocell  
Macrocell  
2
OE  
PTs  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
16  
12  
8
8
16  
8
12  
8
2
2
Programmable  
AND Array  
58 x 188  
8
2
8
16  
2
8
8
12  
16  
12  
OE  
PTs  
2
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
OE  
PTs  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
3
I/O  
1
I/OF  
0
I/OF  
1
I/O  
0
I/O  
2
I/OF  
3
I
-I  
I/O  
3
I/OF  
2
I/OE  
2
0
08740G-1  
Publication# 08740 Rev. G Amendment/0  
Issue Date: June 1993  
2-327  

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