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PALCE20V8Q-20PI/4 PDF预览

PALCE20V8Q-20PI/4

更新时间： 2024-11-09 22:26:31
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑光电二极管输出元件输入元件时钟
页数 文件大小 规格书
27页 500K
描述
EE CMOS 24-Pin Universal Programmable Array Logic

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中文翻译

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PALCE20V8Q-20PI/4 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.300 INCH, SKINNY, PLASTIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.7其他特性：USE GAL DEVICES FOR NEW DESIGNS
架构：PAL-TYPE最大时钟频率：41.6 MHz
JESD-30 代码：R-PDIP-T24JESD-609代码：e0
长度：30.734 mm专用输入次数：12
I/O 线路数量：8输入次数：20
输出次数：8产品条款数：64
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C组织：12 DEDICATED INPUTS, 8 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
可编程逻辑类型：EE PLD传播延迟：20 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

PALCE20V8Q-20PI/4 数据手册

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COM'L: H-5/7/10/15/25, Q-10/15/25  
IND: H-15/25, Q-20/25  
PALCE20V8 Family  
EE CMOS 24-Pin Universal  
Programmable Array Logic  
DISTINCTIVE CHARACTERISTICS  
®
  Pin and function compatible w ith all PAL 20V8 devices  
  Electrically erasable CMOS technology provides reconfigurable logic and full testability  
  High-speed CMOS technology  
— 5-ns propagation delay for “-5” version  
— 7.5-ns propagation delay for “-7” version  
  Direct plug-in replacement for a w ide range of 24-pin PAL devices  
  Programmable enable/disable control  
  Outputs individually programmable as registered or combinatorial  
  Peripheral Component Interconnect (PCI) compliant  
  Preloadable output registers for testability  
  Automatic register reset on pow er-up  
  Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages  
  Extensive third-party softw are and programmer support  
  Fully tested for 100% programming and functional yields and high reliability  
  Programmable output polarity  
  5-ns version utilizes a split leadframe for improved performance  
GENERAL DESCRIPTION  
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-  
erasable CMOS technology. Its macrocells provide a universal device architecture. The  
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series  
devices and most 24-pin combinatorial PAL devices.  
Device logic is automatically configured according to the user’s design specification. A design is  
implemented using any of a number of popular design software packages, allowing automatic  
creation of a programming file based on Boolean or state equations. Design software also verifies  
the design and can provide test vectors for the finished device. Programming can be  
accomplished on standard PAL device programmers.  
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to  
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic  
can always be reduced to sum-of-products form, taking advantage of the very wide input gates  
available in PAL devices. The equations are programmed into the device through floating-gate  
cells in the AND logic array that can be erased electrically.  
Publication# 1 6491  
Amendment/0  
Rev: E  
Issue Date: November 1 998  
1234567...27

中文翻译

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PALCE20V8Q-20PI/4 替代型号

型号 品牌 替代类型 描述 数据表
GAL20V8B-20QPNI LATTICE

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 High Performance E2CMOS PLD Generic Array Log

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