Datasheet > PALCE20V8Q-15PC/4

PALCE20V8Q-15PC/4

更新时间： 2024-11-09 22:26:51

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑光电二极管输出元件输入元件时钟
页数	文件大小	规格书
27页	500K
描述
EE CMOS 24-Pin Universal Programmable Array Logic

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PALCE20V8Q-15PC/4 数据手册

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COM'L: H-5/7/10/15/25, Q-10/15/25

IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible w ith all PAL 20V8 devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for a w ide range of 24-pin PAL devices

Programmable enable/disable control

Outputs individually programmable as registered or combinatorial

Peripheral Component Interconnect (PCI) compliant

Preloadable output registers for testability

Automatic register reset on pow er-up

Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages

Extensive third-party softw are and programmer support

Fully tested for 100% programming and functional yields and high reliability

Programmable output polarity

5-ns version utilizes a split leadframe for improved performance

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. Its macrocells provide a universal device architecture. The

PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series

devices and most 24-pin combinatorial PAL devices.

Device logic is automatically conﬁgured according to the user’s design speciﬁcation. A design is

implemented using any of a number of popular design software packages, allowing automatic

creation of a programming ﬁle based on Boolean or state equations. Design software also veriﬁes

the design and can provide test vectors for the ﬁnished device. Programming can be

accomplished on standard PAL device programmers.

The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ﬂoating-gate

cells in the AND logic array that can be erased electrically.

Publication# 1 6491

Amendment/0

Rev: E

Issue Date: November 1 998

12 3 4 5 6 7...27

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PALCE20V8Q-15PC/4 替代型号

型号	品牌	替代类型	描述	数据表
GAL20V8B-15QPN	LATTICE	功能相似	High Performance E2CMOS PLD Generic Array Log
GAL20V8B-15LPN	LATTICE	功能相似	High Performance E2CMOS PLD Generic Array Log
GAL20V8B-15LP	LATTICE	功能相似	High Performance E2CMOS PLD Generic Array Logic

与PALCE20V8Q-15PC/4相关器件

型号	品牌	获取价格	描述	数据表
PALCE20V8Q-15PC4	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-15PC5	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-15PI	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-15PI4	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-15PI5	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-20JC	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-20JC4	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-20JC5	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-20JI	AMD	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic
PALCE20V8Q-20JI/4	LATTICE	获取价格	EE CMOS 24-Pin Universal Programmable Array Logic

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