PALCE16V8Z-12JI

更新时间： 2024-09-19 22:25:15

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
32页	611K
描述
EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

PALCE16V8Z-12JI 数据手册

PALCE16V8

COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25

IND:-12/15/25

PALCE16V8Z COM’L:-25

PALCE16V8 and PALCE16V8Z Families

EE CMOS (Zero-Power) 20-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible w ith all 20-pin PAL devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for the PAL16R8 series

Outputs programmable as registered or combinatorial in any combination

Peripheral Component Interconnect (PCI) compliant

Programmable output polarity

Programmable enable/disable control

Preloadable output registers for testability

Automatic register reset on pow er up

Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages

Extensive third-party softw are and programmer support

Fully tested for 100% programming and functional yields and high reliability

5-ns version utilizes a split leadframe for improved performance

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The

macrocells provide a universal device architecture. The PALCE16V8 will directly replace the

PAL16R8, with the exception of the PAL16C1.

The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby

current, the PALCE16V8Z allows battery-powered operation for an extended period.

The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ﬂoating-gate

cells in the AND logic array that can be erased electrically.

The ﬁxed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as

registered or combinatorial with an active-high or active-low output. The output conﬁguration

is determined by two global bits and one local bit controlling four multiplexers in each

macrocell.

Publication# 1 6493

Amendment/0

Rev: F

Issue Date: September 2000

12 3 4 5 6 7...32

中文翻译

下载PDF

与PALCE16V8Z-12JI相关器件

型号	品牌	获取价格	描述	数据表
PALCE16V8Z-12PI	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Z-15JC	ETC	获取价格	Electrically-Erasable PLD
PALCE16V8Z-15JI	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Z-15JI/4	LATTICE	获取价格	EE PLD, 15ns, CMOS, PQCC20,
PALCE16V8Z-15JI/5	LATTICE	获取价格	EE PLD, 15ns, CMOS, PQCC20,
PALCE16V8Z-15PC	ETC	获取价格	Electrically-Erasable PLD
PALCE16V8Z-15PI	LATTICE	获取价格	EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
PALCE16V8Z-15PI/4	LATTICE	获取价格	EE PLD, 15ns, CMOS, PDIP20,
PALCE16V8Z20JC	ETC	获取价格	ASIC
PALCE16V8Z20PC	ETC	获取价格	ASIC

与PALCE16V8Z-12JI相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

34
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

31
SL74HC10N：高性能三输入与非门解析
2024-09-03

104
AIC1781A 电池充电控制器深度解析
2024-09-03

99

产品中心

服务支持

精选活动

关于我们

帮助中心

PALCE16V8Z-12JI

PALCE16V8Z-12JI 数据手册

与PALCE16V8Z-12JI相关器件

与PALCE16V8Z-12JI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

PALCE16V8Z-12JI

PALCE16V8Z-12JI 数据手册

与PALCE16V8Z-12JI相关器件

与PALCE16V8Z-12JI相关文章

您还可以找

您在本页遇到什么问题？