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P89LPC931FDH,129

更新时间： 2024-10-27 15:47:27
品牌 Logo 应用领域
恩智浦 - NXP 时钟PC光电二极管外围集成电路
页数 文件大小 规格书
55页 236K
描述
P89LPC930/931 - 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM TSSOP2 28-Pin

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P89LPC931FDH,129 技术参数

Source Url Status Check Date：2013-10-15 00:00:00生命周期：Obsolete
零件包装代码：TSSOP2包装说明：4.40 MM, MO-153, SOT-361-1, PLASTIC, TSSOP-28
针数：28Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.76
具有ADC：NO其他特性：OPERATES AT 2.4V MINIMUM SUPPLY @ 12 MHZ
地址总线宽度：位大小：8
最大时钟频率：18 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：
JESD-30 代码：R-PDSO-G28JESD-609代码：e4
长度：9.7 mm湿度敏感等级：1
I/O 线路数量：26端子数量：28
最高工作温度：85 °C最低工作温度：-45 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not QualifiedROM可编程性：FLASH
座面最大高度：1.1 mm速度：18 MHz
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

P89LPC931FDH,129 数据手册

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P89LPC930/931  
8-bit microcontrollers with two-clock 80C51 core  
4 kB/8 kB 3 V Flash with 256-byte data RAM  
Rev. 05 — 15 December 2004  
Product data  
1. General description  
The P89LPC930/931 are single-chip microcontrollers designed for applications  
demanding high-integration, low cost solutions over a wide range of performance  
requirements. The P89LPC930/931 is based on a high performance processor  
architecture that executes instructions in two to four clocks, six times the rate of  
standard 80C51 devices. Many system-level functions have been incorporated into  
the P89LPC930/931 in order to reduce component count, board space, and system  
cost.  
2. Features  
■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to  
222 ns for all instructions except multiply and divide when executing at 18 MHz.  
This is 6 times the performance of the standard 80C51 running at the same clock  
frequency. A lower clock frequency for the same performance results in power  
savings and reduced EMI.  
■ 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or  
driven to 5.5 V).  
■ 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.  
■ Byte-erase allowing code memory to be used for data storage.  
■ Flash program operation completes in 2 ms.  
■ Flash erase operation completes in 2 ms.  
■ 256-byte RAM data memory.  
■ Two 16-bit counter/timers. Each timer may be configured to toggle a port output  
upon timer overflow or to become a PWM output.  
■ Real-Time clock that can also be used as a system timer.  
■ Two analog comparators with selectable inputs and reference source.  
■ Enhanced UART with fractional baud rate generator, break detect, framing error  
detection, automatic address detection and versatile interrupt capabilities.  
■ 400 kHz byte-wide I2C-bus communication port.  
■ SPI communication port.  
■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.  
■ Four interrupt priority levels.  
■ Watchdog timer with separate on-chip oscillator, requiring no external  
components. The Watchdog time-out time is selectable from 8 values.  
■ Active-LOW reset. On-chip power-on reset allows operation without external reset  
components. A reset counter and reset glitch suppression circuitry prevent  
spurious and incomplete resets. A software reset function is also available.  
 
 
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