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P89LPC932

更新时间: 2024-10-26 21:55:19
品牌 Logo 应用领域
恩智浦 - NXP 闪存微控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
64页 303K
描述
8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM

P89LPC932 数据手册

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P89LPC932A1  
8-bit microcontroller with accelerated two-clock 80C51 core  
8 kB 3 V byte-erasable flash with 512-byte data EEPROM  
Rev. 02 — 10 May 2005  
Product data sheet  
1. General description  
The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based  
on a high performance processor architecture that executes instructions in two to four  
clocks, six times the rate of standard 80C51 devices. Many system-level functions have  
been incorporated into the P89LPC932A1 in order to reduce component count, board  
space, and system cost.  
2. Features  
2.1 Principal features  
8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.  
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.  
256-byte RAM data memory, 512-byte auxiliary on-chip RAM.  
512-byte customer data EEPROM on chip allows serialization of devices, storage of  
set-up parameters, etc.  
Two analog comparators with selectable inputs and reference source.  
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer  
overflow or to become a PWM output) and a 23-bit system timer that can also be used  
as a RTC.  
Enhanced UART with fractional baud rate generator, break detect, framing error  
detection, and automatic address detection; 400 kHz byte-wide I2C-bus  
communication port and SPI communication port.  
CCU provides PWM, input capture, and output compare functions.  
High-accuracy internal RC oscillator option allows operation without external oscillator  
components. The RC oscillator option is selectable and fine tunable.  
2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or  
driven to 5.5 V).  
28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26  
I/O pins while using on-chip oscillator and reset options.  
2.2 Additional features  
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns  
for all instructions except multiply and divide when executing at 18 MHz. This is six  
times the performance of the standard 80C51 running at the same clock frequency. A  
lower clock frequency for the same performance results in power savings and reduced  
EMI.  

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