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P89LPC9301FDH PDF预览

P89LPC9301FDH

更新时间: 2024-10-27 11:52:47
品牌 Logo 应用领域
恩智浦 - NXP 闪存微控制器和处理器外围集成电路光电二极管时钟
页数 文件大小 规格书
65页 297K
描述
8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

P89LPC9301FDH 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, PLASTIC, MO-153, SOT-361, TSSOP-28针数:28
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.82Is Samacsys:N
具有ADC:NO其他特性:ITS ALSO OPERATES MINIMUM 2.4V AT 12 MHZ
地址总线宽度:位大小:8
最大时钟频率:18 MHzDAC 通道:YES
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:R-PDSO-G28JESD-609代码:e4
长度:9.7 mm湿度敏感等级:2
I/O 线路数量:26端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not QualifiedROM可编程性:FLASH
座面最大高度:1.1 mm速度:18 MHz
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

P89LPC9301FDH 数据手册

 浏览型号P89LPC9301FDH的Datasheet PDF文件第2页浏览型号P89LPC9301FDH的Datasheet PDF文件第3页浏览型号P89LPC9301FDH的Datasheet PDF文件第4页浏览型号P89LPC9301FDH的Datasheet PDF文件第5页浏览型号P89LPC9301FDH的Datasheet PDF文件第6页浏览型号P89LPC9301FDH的Datasheet PDF文件第7页 
P89LPC9301/931A1  
8-bit microcontroller with accelerated two-clock 80C51 core  
4 kB/8 kB 3 V byte-erasable flash  
Rev. 01 — 9 April 2009  
Preliminary data sheet  
1. General description  
The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages,  
based on a high performance processor architecture that executes instructions in two to  
four clocks, six times the rate of standard 80C51 devices. Many system-level functions  
have been incorporated into the P89LPC9301/931A1 in order to reduce component count,  
board space, and system cost.  
2. Features  
2.1 Principal features  
I 4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte  
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.  
I 256-byte RAM data memory.  
I Two analog comparators with selectable inputs and reference source.  
I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer  
overflow or to become a PWM output).  
I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit  
prescaler and a programmable and readable 16-bit timer.  
I Enhanced UART with a fractional baud rate generator, break detect, framing error  
detection, and automatic address detection; 400 kHz byte-wide I2C-bus  
communication port and SPI communication port.  
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or  
driven to 5.5 V).  
I Enhanced low voltage (brownout) detect allows a graceful system shutdown when  
power fails.  
I 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins  
while using on-chip oscillator and reset options.  
2.2 Additional features  
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns  
for all instructions except multiply and divide when executing at 18 MHz. This is six  
times the performance of the standard 80C51 running at the same clock frequency. A  
lower clock frequency for the same performance results in power savings and reduced  
EMI.  
I Serial flash In-Circuit Programming (ICP) allows simple production coding with  
commercial EPROM programmers. Flash security bits prevent reading of sensitive  
application programs.  

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