PLL650-02
Low EMI Network LAN Clock
FEATURES
PIN CONFIGURATION
•
Full CMOS output swing with 40-mA output drive
24
23
22
21
20
19
18
17
16
15
14
13
1
2
VDD
VDD
XIN
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
4 outputs at 50MHz, 2 outputs selectable at 25MHz or
125MHz, 1 output selectable at 25MHz or 100MHz.
2 SDRAM selectable frequencies of 66.6, 75, 83.3,
100MHz (Double Drive Strength).
All non SDRAM outputs can be disabled (tri-state)
Spread spectrum technology selectable for EMI
reduction from ±0.5%, ±0.75% for SDRAM and 100MHz
output.
VDD
•
•
•
3
25MHz/100MHz
GND
XOUT/50MHz_OE*^
GND
4
5
SDRAMx2
GND
VDD
•
6
50MHz/FS0*^
GND
7
SDRAMx2
VDD
•
•
8
50MHz/FS1*^
50MHz/FS2*T
FS3T
9
VDD
10
25MHz/125MHz
GND
50MHz/SS0*T 11
•
•
•
•
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
VDD
12
25MHz/125MHz
Note: SDRAMx2: Double Drive strength. T: Tri-Level input ^: Internal pull-up
resistor. *: Bi-directional pin (input value is latched upon power-up).
Available in 24-Pin 150mil SSOP.
DESCRIPTIONS
FREQUENCY TABLE
The PLL 650-02 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25 MHz crystal, and produces multiple output
clocks for networking chips, PCI devices, SDRAM, and
ASICs, with double drive strength for its SDRAM outputs.
FS1
FS0
SDRAM
FS3
Pin 13, 15
FS2
Pin 22
0
0
1
0
1
0
100MHzSST
75MHzSST
83.3MHzSST
0
M
1
Disable
125MHz
25MHz
0
M
1
25MHz
Disable
100MHzSST
FS(2:3): Tri-level inputs.
SST: SST modulation applied (see selection table)
1
1
66.6MHzSST
BLOCK DIAGRAM
4
50MHz
(can be disabled)
XIN
XOUT
XTAL
OSC
2
2
25MHz/125MHz
(can be disabled)
Control
Logic
SDRAM (66.6, 75, 83.3, 100MHz)
FS (0:3)
1
25MHz/100MHz
(can be disabled)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1