Datasheet > P650-05SC

P650-05SC

更新时间： 2024-09-17 09:55:55

品牌	Logo	应用领域
PLL		局域网时钟
页数	文件大小	规格书
6页	231K
描述
Low EMI Network LAN Clock

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数据手册

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P650-05SC 数据手册

PLL650-05

Low EMI Network LAN Clock

FEATURES

PIN CONFIGURATION

•

Full CMOS output swing with 40-mA output drive

XIN

XOUT/ENB_125M*^

GND

VDD

capability. 25-mA output drive at TTL level.

Advanced, low power, sub-micron CMOS processes.

25MHz fundamental crystal or clock input.

3 fixed outputs of 25MHz, 75Mhz and 125Mhz with

output disable

SDRAM selectable frequencies of 105, 83.3, 140MHz

(Double Drive Strength).

Spread spectrum technology selectable for EMI

reduction from ±0.5%, ±0.75% center for SDRAM and

CPU.

•

VDD

25MHz/FS0*^

GND

VDD

•

125MHz

GND

SDRAMx2

VDD

75MHz/FS1*^

ENB_75MHz^

SS0^T

•

Zero PPM synthesis error in all clocks.

Ideal for Network switches.

3.3V operation.

Note: SDRAMx2: Double Drive strength. ^T: Tri-Level input ^: Internal pull-up

resistor *: Bi-directional pin (input value is latched upon power-up).

Available in 16-Pin 150mil SOIC.

FREQUENCY TABLE

DESCRIPTION

FS1

FS0

SDRAMX2

Tristate

140MHz^SST

83.3MHz^SST

105MHz^SST

The PLL650-05 is a low cost, low jitter, high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, this

device can produce multiple clock outputs from a 25.0MHz

crystal or reference clock. This makes the PLL650-05 an

excellent choice for systems requiring clocking for network

chips, PCI devices, SDRAM, and ASICs.

BLOCK DIAGRAM

125MHz

(can be disabled)

XIN

XOUT

XTAL

OSC

SDRAM (105, 83.3, 140MHz)

Control

Logic

75 MHz

(can be disabled)

FS (0:1)

25MHz

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

12 3 4 5 6

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