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P5021NSE72QC PDF预览

P5021NSE72QC

更新时间: 2024-09-17 14:59:23
品牌 Logo 应用领域
恩智浦 - NXP PC双倍数据速率
页数 文件大小 规格书
155页 3042K
描述
QorIQ, 64-Bit Power Arch SoC, 2 X 2.2GHz, DDR3/3L w/ECC, PCIe, 1/10GbE, SATA, SEC, 0 to 90C, Rev 2.1

P5021NSE72QC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred包装说明:BGA,
Reach Compliance Code:compliantECCN代码:5A002.A
HTS代码:8542.31.00.01风险等级:5.24
地址总线宽度:16边界扫描:YES
外部数据总线宽度:64格式:FIXED POINT
集成缓存:YESJESD-30 代码:S-PBGA-B1295
JESD-609代码:e1长度:37.5 mm
低功率模式:YES湿度敏感等级:3
端子数量:1295最高工作温度:105 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):245
座面最大高度:3.53 mm速度:2200 MHz
最大供电电压:1.23 V最小供电电压:1.17 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:37.5 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

P5021NSE72QC 数据手册

 浏览型号P5021NSE72QC的Datasheet PDF文件第2页浏览型号P5021NSE72QC的Datasheet PDF文件第3页浏览型号P5021NSE72QC的Datasheet PDF文件第4页浏览型号P5021NSE72QC的Datasheet PDF文件第5页浏览型号P5021NSE72QC的Datasheet PDF文件第6页浏览型号P5021NSE72QC的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: P5021  
Rev. 1, 05/2014  
P5021  
P5021 QorIQ  
Integrated Processor  
Data Sheet  
FC-PBGA–1295  
37.5 mm × 37.5 mm  
The P5021 QorIQ integrated communication processor  
combines two Power Architecture® processor cores with  
high-performance data path acceleration logic and network  
and peripheral bus interfaces required for networking,  
telecom/datacom, wireless infrastructure, and aerospace  
applications.  
• Two serial ATA (SATA) 2.0 controllers  
• Enhanced secure digital host controller (SD/MMC)  
• Enhanced serial peripheral interface (eSPI)  
• Two high-speed USB 2.0 controllers with integrated PHYs  
• RAID 5 and 6 storage accelerator with support for  
end-to-end data protection information  
• Data Path Acceleration Architecture (DPAA) incorporating  
acceleration for the following functions:  
– Frame Manager (FMan) for packet parsing,  
classification, and distribution  
This chip can be used for combined control, data path, and  
application layer processing in routers, switches, base station  
controllers, and general-purpose embedded computing. Its  
high level of integration offers significant performance  
benefits compared to multiple discrete devices while also  
greatly simplifying board design.  
– Queue Manager (QMan) for scheduling, packet  
sequencing and congestion management  
– Hardware Buffer Manager (BMan) for buffer allocation  
and deallocation  
The chip includes the following function and features:  
– Encryption/Decryption  
• 1295 FC-PBGA package  
• Two e5500 Power Architecture cores  
– Each core has a backside 512 KB L2 cache with ECC  
– Three levels of instructions: user, supervisor, and  
hypervisor  
This figure shows the major functional units within the chip.  
– Independent boot and reset  
– Secure boot capability  
• CoreNet fabric supporting coherent and non-coherent  
transactions amongst CoreNet endpoints  
• Frontside 2 MB CoreNet platform cache with ECC  
• CoreNet bridges between the CoreNet fabric the I/Os,  
datapath accelerators, and high and low speed peripheral  
interfaces  
• Two 10-Gigabit Ethernet (XAUI) controllers  
• Ten 1-Gigabit Ethernet controllers  
– SGMII, 2.5Gb/s SGMII and RGMII interfaces  
• Two 64-bit DDR3/3L SDRAM memory controllers with  
ECC  
• Multicore programmable interrupt controller (PIC)  
2
• Four I C controllers  
• Four 2-pin UARTs or two 4-pin UARTs  
• Two 4-channel DMA engines  
• Enhanced local bus controller (eLBC)  
• Three PCI Express 2.0 controllers/ports  
Freescale reserves the right to change the detail specifications as may be required  
to permit improvements in the design of its products.  
© 2013-2014 Freescale Semiconductor, Inc. All rights reserved.  

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