Datasheet > P5021P5021NSE72QC

P5021P5021NSE72QC

更新时间： 2024-09-17 02:40:07

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
155页	3229K
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P5021 QorIQ Integrated Processor Data Sheet

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: P5021

Rev. 1, 05/2014

P5021

P5021 QorIQ

Integrated Processor

Data Sheet

FC-PBGA–1295

37.5 mm × 37.5 mm

The P5021 QorIQ integrated communication processor

combines two Power Architecture® processor cores with

high-performance data path acceleration logic and network

and peripheral bus interfaces required for networking,

telecom/datacom, wireless infrastructure, and aerospace

applications.

• Two serial ATA (SATA) 2.0 controllers

• Enhanced secure digital host controller (SD/MMC)

• Enhanced serial peripheral interface (eSPI)

• Two high-speed USB 2.0 controllers with integrated PHYs

• RAID 5 and 6 storage accelerator with support for

end-to-end data protection information

• Data Path Acceleration Architecture (DPAA) incorporating

acceleration for the following functions:

– Frame Manager (FMan) for packet parsing,

classification, and distribution

This chip can be used for combined control, data path, and

application layer processing in routers, switches, base station

controllers, and general-purpose embedded computing. Its

high level of integration offers significant performance

benefits compared to multiple discrete devices while also

greatly simplifying board design.

– Queue Manager (QMan) for scheduling, packet

sequencing and congestion management

– Hardware Buffer Manager (BMan) for buffer allocation

and deallocation

The chip includes the following function and features:

– Encryption/Decryption

• 1295 FC-PBGA package

• Two e5500 Power Architecture cores

– Each core has a backside 512 KB L2 cache with ECC

– Three levels of instructions: user, supervisor, and

hypervisor

This figure shows the major functional units within the chip.

– Independent boot and reset

– Secure boot capability

• CoreNet fabric supporting coherent and non-coherent

transactions amongst CoreNet endpoints

• Frontside 2 MB CoreNet platform cache with ECC

• CoreNet bridges between the CoreNet fabric the I/Os,

datapath accelerators, and high and low speed peripheral

interfaces

• Two 10-Gigabit Ethernet (XAUI) controllers

• Ten 1-Gigabit Ethernet controllers

– SGMII, 2.5Gb/s SGMII and RGMII interfaces

• Two 64-bit DDR3/3L SDRAM memory controllers with

ECC

• Multicore programmable interrupt controller (PIC)

• Four I C controllers

• Four 2-pin UARTs or two 4-pin UARTs

• Two 4-channel DMA engines

• Enhanced local bus controller (eLBC)

• Three PCI Express 2.0 controllers/ports

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

12 3 4 5 6 7...155

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