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P502-00DC PDF预览

P502-00DC

更新时间: 2024-09-15 09:56:07
品牌 Logo 应用领域
PLL 晶体石英晶振压控振荡器
页数 文件大小 规格书
4页 180K
描述
Multiplier VCXO IC Die for 12 to 25MHz Parallel Resonant Crystals

P502-00DC 数据手册

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PLL502-00  
Multiplier VCXO IC Die for 12 to 25MHz Parallel Resonant Crystals  
FEATURES  
DIE CONFIGURATION  
65 mil  
Integrated voltage-controlled crystal oscillator  
circuitry (VCXO) (pull range 500ppm minimum).  
Low phase noise (-130dBc @ 10kHz offset at  
44MHz output)  
Selectable frequency multipliers (x1, x2, x4, x8).  
3.3V supply voltage.  
Uses inexpensive fundamental-mode parallel  
resonant crystals (from 12 to 25MHz).  
Selectable High Drive (30mA) or Standard Drive  
(10mA) output.  
(1550,1475)  
25  
23  
21  
20  
19  
18  
Die ID:  
A0707-07A  
C502A  
27  
29  
XIN  
13  
CLK  
XOUT  
Available in DIE (65 mil x 62 mil).  
DESCRIPTION  
10  
GND  
VCON  
31  
The PLL502-00 is a monolithic low jitter and low  
phase noise (-130dBc @10kHz offset at 44MHz  
output), high performance CMOS VCXO IC Die, that  
uses a low cost crystal (12-25MHz).  
The same die can be used as a VCXO with output  
frequencies ranging from FXIN x 1 to FXIN x 8 using  
selector pad bonding options (see Multiplier  
Selection Table on this page). This makes the  
PLL502-00 ideal for a wide range of applications  
from 12MHz to 190MHz (including 27MHz,  
35.328MHz, 77.76MHz and 155.52MHz, etc.).  
7
(0,0)  
Y
Note: ^ denotes internal pull up  
V denotes internal pull down  
X
MULTIPLIER SELECTION  
SELECTION  
FXIN  
CLK (MHz)  
S2  
0
S1  
0
S0  
0
FXIN x 2  
FXIN x 4  
FXIN x 1  
FXIN x 2*  
FXIN x 8  
FXIN x 1*  
FXIN x 4*  
FXIN x 8*  
0
0
1
0
1
0
0
1
1
BLOCK DIAGRAM  
12MHz – 25MHz  
1
0
0
1
0
1
1
1
0
XIN  
Selectable  
1
1
1
VCXO  
CLK  
PLL  
Note: - Selector pads default to ‘0’, wire bond to VDD to set to ‘1’  
- (*) High-drive output  
VCON  
PAD DESCRIPTION  
Name  
Number  
Description  
XIN  
XOUT  
VCON  
GND  
CLK  
27  
29  
Crystal input connection.  
Crystal output connection.  
Voltage Control Input.  
Ground.  
31  
DIE SPECIFICATIONS  
7,10  
Name  
Value  
13  
Clock Output.  
Size  
65 x 62 mil  
GND  
S[0:2]  
VDD  
18,19,20  
21,22,23  
Frequency selection pads  
3.3V Power Supply.  
Reverse side  
Pad dimensions  
Thickness  
80 micron x 80 micron  
10 mil  
Output Enable: ‘0’ to disable (tri-state  
output), 1’ (default value when not  
connected) to enabled the output.  
OE  
25  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1  

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