Datasheet > P502-02SCL

P502-02SCL

更新时间： 2024-09-16 03:43:51

品牌	Logo	应用领域
PLL		振荡器石英晶振压控振荡器
页数	文件大小	规格书
4页	180K
描述
Low Phase Noise VCXO (24MHz to 50MHz)

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中文翻译

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数据手册

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P502-02SCL 数据手册

PLL502-02

Low Phase Noise VCXO (24MHz to 50MHz)

FEATURES

PIN CONFIGURATION

•

Low phase noise VCXO output for the 24MHz to

50MHz range (-130 dBc at 10kHz offset).

CMOS output.

XOUT

N/C

XIN

•

12 to 25MHz crystal input.

Integrated variable capacitors.

Selectable High Drive (30mA) or Standard Drive

(10mA) output.

Wide pull range (+/- 250 ppm typ.).

Low jitter (RMS): 3ps period (1 sigma).

3.3V operation.

N/C

VDD

CLK

VCON

GND

•

Available in 8-Pin SOIC.

DESCRIPTION

OUTPUT RANGE

The PLL502-02 is a low cost, high performance, low

phase noise VCXO, providing less than -130dBc at

10kHz offset in the 24MHz to 50MHz operating

range. The very low jitter (3 ps RMS period jitter)

makes this chip ideal for applications requiring volt-

age controlled frequency sources. Input crystal can

range from 12 to 25MHz (fundamental resonant

mode).

FREQUENCY

OUTPUT

BUFFER

MULTIPLIER

RANGE

24 - 50MHz

CMOS

BLOCK DIAGRAM

VCO

Divider

Reference

Divider

Phase

Charge

Pump

Loop

Filter

VCO

Comparator

CLK

XIN

XOUT

XTAL

OSC

VARICAP

VCON

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/14/05 Page 1

12 3 4

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