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P4C163-35CMLF PDF预览

P4C163-35CMLF

更新时间: 2024-11-18 04:55:11
品牌 Logo 应用领域
PYRAMID 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 322K
描述
ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS

P4C163-35CMLF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:28
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.11
Is Samacsys:N最长访问时间:35 ns
JESD-30 代码:R-CDIP-T28内存密度:73728 bit
内存集成电路类型:STANDARD SRAM内存宽度:9
功能数量:1端子数量:28
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:8KX9
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:5.715 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

P4C163-35CMLF 数据手册

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P4C163/P4C163L  
ULTRA HIGH SPEED 8K x 9  
STATIC CMOS RAMS  
FEATURES  
Data Retention with 2.0V Supply, 10 µA Typical  
Current (P4C163L Military)  
Full CMOS, 6T Cell  
High Speed (Equal Access and Cycle Times)  
– 25/35ns (Commercial)  
Common I/O  
– 25/35/45ns (Military)  
Fully TTL Compatible Inputs and Outputs  
Low Power Operation (Commercial/Military)  
Standard Pinout (JEDEC Approved)  
– 28-Pin 300 mil DIP, SOJ  
– 28-Pin 350 x 550 mil LCC  
– 28-Pin CERPACK  
Output Enable and Dual Chip Enable Control  
Functions  
Single 5V±10% Power Supply  
DESCRIPTION  
Accesstimesasfastas25nanosecondsareavailable,per-  
mittinggreatlyenhancedsystemoperatingspeeds.CMOS  
is used to reduce power consumption in both active and  
standbymodes.  
TheP4C163andP4C163Lare73,728-bitultrahigh-speed  
staticRAMsorganizedas8Kx9.TheCMOSmemoriesre-  
quire no clocks or refreshing and have equal access and  
cycle times. Inputs are fully TTL-compatible. The RAMs  
operate from a single 5V±10% tolerance power supply.  
Withbatterybackup,dataintegrityismaintainedforsupply  
voltages down to 2.0V. Current drain is 10 µA from a 2.0V  
supply.  
The P4C163 and P4C163L are available in 28-pin 300 mil  
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin  
CERPACKpackagesprovidingexcellentboardleveldensi-  
ties.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATIONS  
DIP (P5, C5), SOJ (J5)  
CERPACK (F4) SIMILAR  
LCC (L5)  
Document # SRAM120 REV C  
Revised August 2006  
1

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