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P4C163-35JM PDF预览

P4C163-35JM

更新时间: 2024-11-18 04:55:11
品牌 Logo 应用领域
PYRAMID /
页数 文件大小 规格书
12页 322K
描述
ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS

P4C163-35JM 数据手册

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P4C163/P4C163L  
ULTRA HIGH SPEED 8K x 9  
STATIC CMOS RAMS  
FEATURES  
Data Retention with 2.0V Supply, 10 µA Typical  
Current (P4C163L Military)  
Full CMOS, 6T Cell  
High Speed (Equal Access and Cycle Times)  
– 25/35ns (Commercial)  
Common I/O  
– 25/35/45ns (Military)  
Fully TTL Compatible Inputs and Outputs  
Low Power Operation (Commercial/Military)  
Standard Pinout (JEDEC Approved)  
– 28-Pin 300 mil DIP, SOJ  
– 28-Pin 350 x 550 mil LCC  
– 28-Pin CERPACK  
Output Enable and Dual Chip Enable Control  
Functions  
Single 5V±10% Power Supply  
DESCRIPTION  
Accesstimesasfastas25nanosecondsareavailable,per-  
mittinggreatlyenhancedsystemoperatingspeeds.CMOS  
is used to reduce power consumption in both active and  
standbymodes.  
TheP4C163andP4C163Lare73,728-bitultrahigh-speed  
staticRAMsorganizedas8Kx9.TheCMOSmemoriesre-  
quire no clocks or refreshing and have equal access and  
cycle times. Inputs are fully TTL-compatible. The RAMs  
operate from a single 5V±10% tolerance power supply.  
Withbatterybackup,dataintegrityismaintainedforsupply  
voltages down to 2.0V. Current drain is 10 µA from a 2.0V  
supply.  
The P4C163 and P4C163L are available in 28-pin 300 mil  
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin  
CERPACKpackagesprovidingexcellentboardleveldensi-  
ties.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATIONS  
DIP (P5, C5), SOJ (J5)  
CERPACK (F4) SIMILAR  
LCC (L5)  
Document # SRAM120 REV C  
Revised August 2006  
1

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