Datasheet > ORSO82G5-3FN680C

ORSO82G5-3FN680C

更新时间： 2024-11-05 03:44:47

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
153页	1628K
描述
0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

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ORSO82G5-3FN680C 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	PGA	包装说明：	LEAD FREE, FPGA-680
针数：	680	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-XBGA-B680
JESD-609代码：	e1	湿度敏感等级：	3
可配置逻辑块数量：	1226	等效关口数量：	333000
端子数量：	680	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	1226 CLBS, 333000 GATES
封装主体材料：	UNSPECIFIED	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	250	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
Base Number Matches：	1

ORSO82G5-3FN680C 数据手册

ORCA^®ORSO42G5 and ORSO82G5

0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

July 2008

Data Sheet DS1028

Introduction

Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5

devices. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and

ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbps and 20 Gbps respectively.

These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non-

SONET applications.The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6-

2.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable

FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already

been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces.

With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design-

ers can build a conﬁgurable interface using proven backplane driver/receiver technology. Designers can also use

the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The

ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbps backplane data connection and, with the

ORSO82G5, support both work and protection connections between a line card and switch fabric.

The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a

board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system

performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network

designers will beneﬁt from using the backplane transceiver as a network termination device. Sister devices, the

ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet

(XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling,

streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi-

nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes

them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET

applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The

ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.

Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic

FPGA

PFU

FPGA Max

User I/O

EBR

EBR Bits

(K)

System

Device

ORSO42G5

ORSO82G5

PFU Rows Columns Total PFUs

LUTs

10,368

Blocks²

Gates (K)¹

1296

204

372

111

333-643

1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate

ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with

40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%

EBR usage and 4 PLLs.

2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

DS1028_08.0

12 3 4 5 6 7...153

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