Datasheet > ORSPI4-2F1156C

ORSPI4-2F1156C

更新时间： 2024-11-06 03:43:27

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
263页	1195K
描述
Dual SPI4 Interface and High-Speed SERDES FPSC

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技术参数
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ORSPI4-2F1156C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	35 X 35 MM, FPBGA-1156
针数：	1156	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.83	最大时钟频率：	185 MHz
JESD-30 代码：	S-PBGA-B1156	JESD-609代码：	e0
长度：	35 mm	湿度敏感等级：	3
可配置逻辑块数量：	2024	等效关口数量：	471000
端子数量：	1156	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	2024 CLBS, 471000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.6 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	35 mm	Base Number Matches：	1

ORSPI4-2F1156C 数据手册

ORCA^®ORSPI4

Dual SPI4 Interface

and High-Speed SERDES FPSC

October 2007

Data Sheet

Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on

the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two

SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b

encoding and decoding and over 600K programmable system gates all on a single chip.

■

Simple FIFO interface to the FPGA logic

Embedded SPI4 Core Features

• Provides ease of design and efﬁcient clock

■

OIF-SPI4-02.0 compliant interfaces

domain transfers

■

Dynamic timing receive interface:

■

Loopback modes provided for system- and

chip-level debug

• Full bandwidth up to 450 MHz DDR (900

Mbits/s) for all speed grades.

Embedded 32-bit internal system bus plus 4-bit

parity

• Interconnects FPGA logic, microprocessor inter-

face (MPI), embedded RAM blocks, and embed-

ded core blocks

• Includes built-in system registers that act as the

control and status center for the device

• Bit de-skewing up to 16 phases of the clock

• Capable of aligning bit-to-bit skews as large as

1 bit periods

■

Static timing receive interface:

• Speeds up to 325 MHz DDR (650 Mbits/s), for

all speed grades, including Quarter-Rate mode

• Clock aligned or clock centered modes sup-

ported

■

Low power operation.

• Full-rate SPI4.2 interfaces running at 450 MHz

DDR (900 Mbits/sec) with dynamic alignment

consumes 1.5 W of power or less. More efﬁcient

than FPGAs with soft-IP SPI4 solutions which

consume in excess of 10 W.

■

DIP-4 and DIP-2 parity generation and checking

Transmit Interface:

• Speeds up to 450 MHz DDR (900 Mbits/s)

• Dedicated LVDS transmit interface for improved

data eye integrity

• Automatic idle insertion

■

Programmable Minburst capability with

selectable burst values ranging from 16 to 240.

Interoperability demonstrated with ORSPI4

partners.

■

256 logical ports:

• Embedded Calendar-based sequence port poll-

ing mechanism and bandwidth allocation.

Shadow Calendar support for smooth transition

to new Calendar

Embedded SERDES Core Features

■

Quad 600 Mbits/s to 3.7 Gbits/s SERDES:

• IEEE 802.3ae XAUI (Link State Machine &

• Up to 32 independent TX and 32 independent

RX buffers per SPI4 interface internally. Various

aggregation modes to support 1 to 32 separate

embedded buffers per TX and RX

• Up to 4 independent TX and 4 independent RX

clock domain transfers to the FPGA logic

Alignment FIFOs embedded)

• ANSI X3.230:1994 1G/2G FC-compliant (Link

State Machine & Alignment FIFOs embedded)

• Proven performance (same SERDES used in

ORT82G5/ORT42G5 FPSCs)

Embedded Memory Controller Features

■

FIFO status support modes:

• 1/4 rate LVTTL or 1/4 rate LVDS

• Automatic status handling or optionally under

user control. Credit calculations based on burst

size and status are also handled automatically

■

High Performance Memory Controller for

interface to external buffer memory

• Required for Layer 2 data buffering

• QDR II memory interface:

– 36-bit Input and 36-bit Output bus, 18-bit address

– 175 MHz clock rates

Conﬁguration options as suggested in the OIF-

SPI4-02.0 standard

• Conﬁgures parameters such as maximum burst

– 20+ Gbits/s bandwidth

– Supports 2- or 4-word burst mode

– Simple FIFO interface to FPGA

– Integrated PLL for optimized performance

– Proven performance with multiple memory suppliers

size, calendar length, main and shadow calen-

dars (1K deep each), length of training

sequence etc.

Note: The term SPI4 refers to OIF SPI-4.2 throughout this document

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

ORSPI4_06

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与ORSPI4-2F1156C相关器件

型号	品牌	获取价格	描述	数据表
ORSPI4-2F1156I	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-2FE1036C	LATTICE	获取价格	Micro Peripheral IC, PBGA1036
ORSPI4-2FE1036C2	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-2FE1036CES	LATTICE	获取价格	Micro Peripheral IC
ORSPI4-2FE1036I	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-2FN1156C	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-2FN1156I	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-2FTE1036C	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-2FTE1036I	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-3F1156C	LATTICE	获取价格	Dual SPI4 Interface and High-Speed SERDES FPSC

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