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OR4E04-1BMN680C

更新时间： 2024-11-18 19:56:55
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟栅可编程逻辑
页数 文件大小 规格书
158页 823K
描述
Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA680, PLASTIC, FBGA-680

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OR4E04-1BMN680C 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：680
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
其他特性：MAXIMUM NO OF USABLE GATES IS 643000最大时钟频率：420 MHz
CLB-Max的组合延迟：1.1 nsJESD-30 代码：S-PBGA-B680
长度：35 mm可配置逻辑块数量：1296
等效关口数量：333000端子数量：680
最高工作温度：70 °C最低工作温度：
组织：1296 CLBS, 333000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
座面最大高度：2.51 mm最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：35 mmBase Number Matches：1

OR4E04-1BMN680C 数据手册

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Data Sheet  
November, 2003  
®
ORCA Series 4 FPGAs  
■ Traditional I/O selections:  
— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)  
I/Os.  
Introduction  
Built on the Series 4 reconfigurable embedded sys-  
tem-on-a-chip (SoC) architecture, Lattice introduces  
its new family of generic Field-Programmable Gate  
Arrays (FPGAs). The high-performance and highly  
versatile architecture brings a new dimension to  
bringing network system designs to market in less  
time than ever before. This new device family offers  
many new features and architectural enhancements  
not available in any earlier FPGA generations. Bring-  
ing together highly flexible SRAM-based programma-  
ble logic, powerful system features, a rich hierarchy  
of routing and interconnect resources, and meeting  
multiple interface standards, the Series 4 FPGA  
accommodates the most complex and high-perfor-  
mance intellectual property (IP) network designs.  
— Per pin-selectable I/O clamping diodes provide  
3.3 V PCI compliance.  
— Individually programmable drive capability:  
24 mA sink/12 mA source, 12 mA sink/6 mA  
source, or 6 mA sink/3 mA source.  
— Two slew rates supported (fast and slew-lim-  
ited).  
— Fast-capture input latch and input flip-flop  
(FF)/latch for reduced input setup time and zero  
hold time.  
— Fast open-drain drive capability.  
— Capability to register 3-state enable signal.  
— Off-chip clock drive capability.  
— Two-input function generator in output path.  
■ New programmable high-speed I/O:  
— Single-ended: GTL, GTL+, PECL, SSTL3/2  
(class I and II), HSTL (Class I, III, and IV), ZBT,  
and DDR.  
— Double-ended: LDVS, bused-LVDS, and  
LVPECL. Programmable (on/off) internal parallel  
termination (100 Ω) also supported for these  
I/Os.  
Programmable Features  
■ High-performance platform design:  
— 0.16 µm 7-level metal technology.  
— Internal performance of >250 MHz.  
— I/O performance of >420 MHz.  
— Meets multiple I/O interface standards.  
— 1.5 V operation (30% less power than 1.8 V  
operation) translates to greater performance.  
Table 1. ORCA Series 4—Available FPGA Logic  
EBR  
Blocks  
EBR Bits  
(K)  
Usable*  
Gates (K)  
Device  
Rows  
Columns  
PFUs  
User I/O  
LUTs  
OR4E02  
OR4E04  
OR4E06  
26  
36  
46  
24  
36  
44  
624  
405  
466  
466  
4,992  
10,368  
16,192  
8
74  
201—397  
333—643  
471—899  
1,296  
2,024  
12  
16  
111  
148  
* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:  
minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum  
system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.  
Note: Devices are not pinout compatible with ORCA Series 2/3.  
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All  
other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to  
change without notice.  
www.latticesemi.com  
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