Datasheet > OR4E04-2BM680I

OR4E04-2BM680I

更新时间： 2024-11-21 03:44:47

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
152页	2702K
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ORCASeries 4 FPGAs

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OR4E04-2BM680I 数据手册

Data Sheet

May, 2006

ORCA Series 4 FPGAs

■ Traditional I/O selections:

— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)

I/Os.

Introduction

Built on the Series 4 reconﬁgurable embedded sys-

tem-on-a-chip (SoC) architecture, Lattice introduces

its new family of generic Field-Programmable Gate

Arrays (FPGAs). The high-performance and highly

versatile architecture brings a new dimension to

bringing network system designs to market in less

time than ever before. This new device family offers

many new features and architectural enhancements

not available in any earlier FPGA generations. Bring-

ing together highly ﬂexible SRAM-based programma-

ble logic, powerful system features, a rich hierarchy

of routing and interconnect resources, and meeting

multiple interface standards, the Series 4 FPGA

accommodates the most complex and high-perfor-

mance intellectual property (IP) network designs.

— Per pin-selectable I/O clamping diodes provide

3.3 V PCI compliance.

— Individually programmable drive capability:

24 mA sink/12 mA source, 12 mA sink/6 mA

source, or 6 mA sink/3 mA source.

— Two slew rates supported (fast and slew-lim-

ited).

— Fast-capture input latch and input ﬂip-ﬂop

(FF)/latch for reduced input setup time and zero

hold time.

— Fast open-drain drive capability.

— Capability to register 3-state enable signal.

— Off-chip clock drive capability.

— Two-input function generator in output path.

■ New programmable high-speed I/O:

— Single-ended: GTL, GTL+, PECL, SSTL3/2

(class I and II), HSTL (Class I, III, and IV), ZBT,

and DDR.

— Double-ended: LDVS, bused-LVDS, and

LVPECL. Programmable (on/off) internal parallel

termination (100 Ω) also supported for these

I/Os.

Programmable Features

■ High-performance platform design:

— 0.16 μm 7-level metal technology.

— Internal performance of >250 MHz.

— I/O performance of >420 MHz.

— Meets multiple I/O interface standards.

— 1.5 V operation (30% less power than 1.8 V

operation) translates to greater performance.

Table 1. ORCA Series 4—Available FPGA Logic

EBR

Blocks

EBR Bits

(K)

Usable*

Gates (K)

Device

Rows

Columns

PFUs

User I/O

LUTs

OR4E02

OR4E04

OR4E06

624

405

466

4,992

10,368

16,192

201—397

333—643

471—899

1,296

2,024

111

148

* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:

minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum

system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.

Note: Devices are not pinout compatible with ORCA Series 2/3.

other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to

change without notice.

www.latticesemi.com

or4e_05

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与OR4E04-2BM680I相关器件

型号	品牌	获取价格	描述	数据表
OR4E04-2BMN416C	LATTICE	获取价格	Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA416, PLASTIC, FB
OR4E04-2BMN416I	LATTICE	获取价格	Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA416, PLASTIC, FB
OR4E04-3BA352C	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E04-3BAN352C	LATTICE	获取价格	Field Programmable Gate Array, 1296 CLBs, 333000 Gates, 420MHz, CMOS, PBGA352, PLASTIC, BG
OR4E04-3BM416C	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E04-3BM680C	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E06	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E06-1BA352C	LATTICE	获取价格	ORCASeries 4 FPGAs
OR4E061BA352-DB	LATTICE	获取价格	Field Programmable Gate Array, 2024 CLBs, 515000 Gates, 66MHz, 16192-Cell, CMOS, PBGA352,
OR4E06-1BA352I	LATTICE	获取价格	ORCASeries 4 FPGAs

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