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OR4E04-3BM680C

更新时间： 2024-11-18 03:44:47
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
152页 2702K
描述
ORCASeries 4 FPGAs

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OR4E04-3BM680C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, FBGA-680
针数：680Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.85其他特性：MAXIMUM NO OF USABLE GATES IS 643000
最大时钟频率：420 MHzCLB-Max的组合延迟：0.74 ns
JESD-30 代码：S-PBGA-B680JESD-609代码：e0
长度：35 mm湿度敏感等级：3
可配置逻辑块数量：1296等效关口数量：333000
输入次数：466逻辑单元数量：10368
输出次数：466端子数量：680
最高工作温度：70 °C最低工作温度：
组织：1296 CLBS, 333000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA680,34X34,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.5/3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.51 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.575 V最小供电电压：1.425 V
标称供电电压：1.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：35 mm

OR4E04-3BM680C 数据手册

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Data Sheet  
May, 2006  
®
ORCA Series 4 FPGAs  
■ Traditional I/O selections:  
— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)  
I/Os.  
Introduction  
Built on the Series 4 reconfigurable embedded sys-  
tem-on-a-chip (SoC) architecture, Lattice introduces  
its new family of generic Field-Programmable Gate  
Arrays (FPGAs). The high-performance and highly  
versatile architecture brings a new dimension to  
bringing network system designs to market in less  
time than ever before. This new device family offers  
many new features and architectural enhancements  
not available in any earlier FPGA generations. Bring-  
ing together highly flexible SRAM-based programma-  
ble logic, powerful system features, a rich hierarchy  
of routing and interconnect resources, and meeting  
multiple interface standards, the Series 4 FPGA  
accommodates the most complex and high-perfor-  
mance intellectual property (IP) network designs.  
— Per pin-selectable I/O clamping diodes provide  
3.3 V PCI compliance.  
— Individually programmable drive capability:  
24 mA sink/12 mA source, 12 mA sink/6 mA  
source, or 6 mA sink/3 mA source.  
— Two slew rates supported (fast and slew-lim-  
ited).  
— Fast-capture input latch and input flip-flop  
(FF)/latch for reduced input setup time and zero  
hold time.  
— Fast open-drain drive capability.  
— Capability to register 3-state enable signal.  
— Off-chip clock drive capability.  
— Two-input function generator in output path.  
■ New programmable high-speed I/O:  
— Single-ended: GTL, GTL+, PECL, SSTL3/2  
(class I and II), HSTL (Class I, III, and IV), ZBT,  
and DDR.  
— Double-ended: LDVS, bused-LVDS, and  
LVPECL. Programmable (on/off) internal parallel  
termination (100 Ω) also supported for these  
I/Os.  
Programmable Features  
■ High-performance platform design:  
— 0.16 μm 7-level metal technology.  
— Internal performance of >250 MHz.  
— I/O performance of >420 MHz.  
— Meets multiple I/O interface standards.  
— 1.5 V operation (30% less power than 1.8 V  
operation) translates to greater performance.  
Table 1. ORCA Series 4—Available FPGA Logic  
EBR  
Blocks  
EBR Bits  
(K)  
Usable*  
Gates (K)  
Device  
Rows  
Columns  
PFUs  
User I/O  
LUTs  
OR4E02  
OR4E04  
OR4E06  
26  
36  
46  
24  
36  
44  
624  
405  
466  
466  
4,992  
10,368  
16,192  
8
74  
201—397  
333—643  
471—899  
1,296  
2,024  
12  
16  
111  
148  
* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:  
minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum  
system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.  
Note: Devices are not pinout compatible with ORCA Series 2/3.  
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All  
other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to  
change without notice.  
www.latticesemi.com  
1
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